Nonvolatile Memory Device Programming Reliability via Fail Bit Detection

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Solution Overview

Problem

Current flash memory devices face challenges in improving integration density and reducing error bits during programming operations, leading to inefficiencies in storage capacity and reliability.

Innovation Solution

A method for programming nonvolatile memory devices that involves applying program pulses, detecting fail bits, and determining program completion based on the number of failed and disturbed bits, with multiple program loops until the number of fail bits falls below a predetermined value, and using a page buffer circuit to store and verify program bits and inhibit bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple program loops are performed to reduce error bits, then programming reliability is improved, but programming time and energy consumption increase

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a feedback mechanism where the number of fail bits is detected after each program loop, and the control logic uses this information to determine whether to continue programming or terminate the operation. This allows the system to adapt the number of program loops based on actual programming success, avoiding unnecessary additional loops while ensuring reliability when needed.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent makes the programming process dynamic by adjusting the number of program loops based on real-time fail bit detection. Instead of using a fixed number of loops, the system dynamically determines when to stop based on whether the fail bit count falls below the reference value, optimizing both time and reliability.

Inventive Principle:

Principle #15Dynamics

2Manufacturing precision

If the reference value for fail bits is lowered to improve data integrity, then programming precision is improved, but the number of program loops increases

Engineering Contradiction:

Improveprogramming precisionVSAvoidprogramming efficiency

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent changes the parameter of reference value based on the current programming state and fail bit detection. The control logic adjusts whether to continue programming based on the relationship between the current fail bit count and the reference value, allowing the system to optimize precision without unnecessarily increasing program loops.

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If inhibition bits are not properly managed, then device complexity is reduced, but programming reliability deteriorates due to disturbed bits

Engineering Contradiction:

Improvecontrol logic complexityVSAvoidprogramming reliability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent merges the detection of failed program bits and disturbed inhibit bits into a single fail bit count mechanism. By combining these two types of errors into one detection process, the system maintains reliability in managing inhibition bits while avoiding the complexity of separate detection and correction mechanisms for each error type.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8427871B2Nonvolatile memory device, memory system incorporating same, and method of operating same

Publication Date: 2013.04.23 SAMSUNG ELECTRONICS CO LTD

AI summary

A nonvolatile memory device performs a program operation comprising applying a program pulse to selected memory cells, detecting a number of fail bits among the selected memory cells, the fail bits comprising failed program bits and disturbed inhibit bits, and determining a program completion status of the program operation based on the number of detected fail bits.