Non-volatile Memory Floating Gate Corner Erase Gate
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to reduced gate length in non-volatile memory cells, causing abnormal punch-through and wear of the tunneling oxide layer, which affects electrical performance and reliability.
Innovation Solution
A non-volatile memory design with a floating gate having a notch and an erase gate covering the corner, along with a high-k metal gate (HKMG) process, increases the gate-coupling ratio and reduces gate resistance, enhancing operational speed and integration level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced to increase integration level, then the level of integration is improved, but abnormal punch-through occurs and reliability deteriorates
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate, second gate, third gate, fourth gate) arranged in sequence over the channel. This segmentation allows each gate to independently control different portions of the channel, preventing punch-through while maintaining short overall gate length for high integration.
Solution Approach 2:
The invention transitions from a single-plane gate structure to a multi-layer stacked gate structure extending in the vertical dimension. Multiple gates are disposed at different heights and positions, creating a three-dimensional gate arrangement that enhances channel control without increasing lateral footprint, thus maintaining high integration.
2Productivity
If the gate length is reduced to increase integration level, then the level of integration is improved, but the tunneling oxide layer wears off and reliability deteriorates
Solution Approach 1:
The tunneling oxide layer is segmented into multiple separate layers (first tunneling oxide layer, second tunneling oxide layer, third tunneling oxide layer) positioned between different gate structures. This segmentation distributes the electron tunneling stress across multiple layers, preventing wear of a single layer and enhancing reliability while maintaining short gate length for high integration.
Solution Approach 2:
Multiple tunneling oxide layers are positioned in sequence between the stacked gates and the charge trapping layer, creating a cushioning effect that distributes and reduces the cumulative damage from repeated electron tunneling during programming and erasing operations, thereby protecting against oxide layer wear.
3Speed
If the dielectric layer thickness is reduced to increase gate-coupling ratio, then operational speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The invention changes the dielectric parameter by using a high-k dielectric material with dielectric constant greater than 4 in the inter-gate dielectric layer. This parameter change allows for thicker dielectric layers while maintaining high gate-coupling ratio, thus improving operational speed without increasing manufacturing precision requirements.
4Speed
If metal silicide or metal gate is used to reduce gate resistance, then operational speed is improved, but device complexity increases
Solution Approach 1:
The invention merges multiple gate structures (first gate, second gate, third gate, fourth gate) into a unified stacked gate assembly that functions as an integrated control system. This merging reduces the overall gate resistance by providing multiple parallel conduction paths while maintaining manageable device complexity through systematic arrangement.
Solution Approach 2:
The gate structures use composite material construction with polysilicon layers combined with metal silicide regions. This composite approach reduces gate resistance to improve operational speed while managing complexity through established fabrication processes for polycide structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for efficient data erasure at lower voltages, increased transistor capacitance, and improved device performance by concentrating the electrical field and reducing gate leakage and threshold voltage.
Implementation Method 1
electrons are injected into a polysilicon floating gate or pulled out from the polysilicon floating gate
Implementation Method 2
increasing the dielectric constant (k) of the inter-gate dielectric layer between the floating gate and the control gate
Implementation Method 3
concentrating the electrical field
Data Source
AI summary
A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.