Non-volatile Memory Floating Gate Finger Structure
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Solution Overview
Problem
Current non-volatile memory devices face challenges in achieving high integration density due to the need for additional processes and complex structures, which hinder their application in embedded memory systems, especially in System on Chip (SoC) technology.
Innovation Solution
A non-volatile memory device design that includes a floating gate with multiple fingers, an active control gate, and control plugs, which are electrically connected through a control unit to control the bias applied to the active control gate, allowing for improved coupling ratios in a minimal area without requiring additional fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional fabrication processes are used to improve integration density, then the integration degree improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The floating gate is divided into multiple fingers that extend in the first direction, allowing the memory cell to achieve higher integration density without requiring additional fabrication processes. The segmented floating gate structure enables better coupling ratios while maintaining compatibility with existing CMOS logic processes.
Solution Approach 2:
The invention extends the floating gate structure in the first direction (horizontal dimension) rather than increasing vertical stacking, thereby improving integration density within the planar area without adding process complexity. The control plugs are positioned at specific locations along this extended structure to provide necessary electrical connections.
2Quantity of substance
If additional fabrication processes are used to improve integration density, then the integration degree improves, but the ease of manufacture deteriorates
Solution Approach 1:
The memory cell structure is designed to be fabricated using standard CMOS logic processes, making the same fabrication equipment and process steps applicable to both logic circuits and memory cells. This universal approach eliminates the need for dedicated memory fabrication processes, thereby improving ease of manufacture while achieving high integration density.
Solution Approach 2:
The invention combines the memory cell structure with standard CMOS logic circuit fabrication processes. The floating gate, control gate, and control plugs are formed using the same process steps as logic transistors, merging memory and logic manufacturing into a single unified process flow.
3Reliability
If the floating gate structure is extended to improve coupling ratio, then the coupling ratio improves, but the area occupied increases
Solution Approach 1:
Control plugs are strategically positioned at specific locations along the extended floating gate structure to provide localized electrical connections. This local quality approach ensures adequate coupling ratio at critical points without requiring the entire floating gate structure to be excessively large, thereby optimizing the balance between coupling ratio and cell area.
Solution Approach 2:
The floating gate fingers are pre-positioned and connected to control plugs before final device operation. This preliminary action ensures that the coupling structure is optimized in advance, allowing the device to achieve high coupling ratio without requiring excessive area during actual memory operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the integration density of non-volatile memory devices, simplifies the data programming and erasing structure, and allows for the use of various operation schemes like hot carrier injection and Fowler-Nordheim tunneling, while reducing the complexity of the peripheral circuitry.
Implementation Method 1
a control unit which electrically connects the active control gate to the control plugs and controls a bias applied to the active control gate
Implementation Method 2
allows for the use of various operation schemes like hot carrier injection and Fowler-Nordheim tunneling
Implementation Method 3
allows for the use of various operation schemes like hot carrier injection and Fowler-Nordheim tunneling
Data Source
AI summary
A non-volatile memory device includes: a floating gate having a plurality of fingers; a first coupling unit including an active control gate which overlaps with the floating gate in a vertical direction; a second coupling unit including a plurality of control plugs which overlap with the floating gate in a horizontal direction; and a control unit which electrically connects the active control gate to the control plugs and controls a bias to be applied to the active control gate.