Nonvolatile Memory Gate Patterning via Single Photo Etching
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Solution Overview
Problem
The existing nonvolatile memory devices require multiple photo etching processes to form memory transistors, increasing processing time and cost due to the separation and patterning of floating and control gates.
Innovation Solution
A nonvolatile memory device structure where the floating gate and control gate are patterned in a single photo-etching process, reducing the number of processing steps and eliminating the need for additional photo etching to separate the control gates, with metal interconnections connecting the control gates and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photo etching processes are used to separate floating gate and control gate, then manufacturing precision is improved, but processing time and device complexity increase
Solution Approach 1:
The patent merges the patterning of floating gate and control gate into a single photo etching process. By forming both gates simultaneously using one photoresist layer and one etching step, the invention eliminates the need for separate photo etching processes that would otherwise be required to pattern each gate independently, thereby reducing processing time while maintaining manufacturing precision
Solution Approach 2:
The photoresist layer serves multiple functions: it patterns both the floating gate and control gate, and also defines the bit line regions. This multi-functional approach allows a single photo etching process to accomplish what would traditionally require multiple separate processes, reducing both time and complexity
2Manufacturing precision
If multiple photo etching processes are used to form memory transistor gates, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The invention combines multiple gate patterning operations into a single photo etching step. By using a unified photoresist pattern that simultaneously defines floating gates, control gates, and bit line regions, the process complexity is reduced from multiple sequential photo etching steps to a single integrated process step
Solution Approach 2:
The photoresist layer is segmented into different regions (first photoresist layer for floating gate, second photoresist layer for control gate and bit line) that are processed together in one etching step. This segmentation allows complex multi-gate structures to be formed through a single process operation rather than multiple separate operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing steps and costs by integrating the patterning of floating and control gates, enabling efficient manufacturing of nonvolatile memory devices with reduced complexity and time.
Implementation Method 1
charge is stored in a floating gate after passing through a thin insulating layer, i.e., a tunnel oxide layer, comprising an insulating material such as SiO2, by a Fowler-Nordheim tunneling phenomenon
Data Source
AI summary
A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection.