Non-volatile Memory Gate Structure Simplification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of non-volatile memory devices with multiple gate structures is complex and involves numerous steps, including the formation of multiple mask layers, which complicates the overall process.
Innovation Solution
A non-volatile memory device design featuring three gate structures, where the memory gate structure includes a charge storage layer with an oxide/nitride/oxide (ONO) structure, covering the first and second gate structures, and a spacer on the sidewalls, simplifies the manufacturing process by omitting some steps in forming mask layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple gate structures are formed with separate mask layers, then manufacturing precision is improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent combines the formation of multiple gate structures (first gate structure, second gate structure, and memory gate structure) into a single manufacturing process step. A common mask layer is used to define all three gate structures simultaneously, eliminating the need for separate mask formation steps for each gate. This merging approach reduces process complexity while maintaining the required structural precision through the unified masking process.
Solution Approach 2:
The common mask layer serves multiple functions: it defines the first gate structure, the second gate structure, and the memory gate structure all in one step. This universal mask layer approach allows a single masking operation to accomplish what would traditionally require multiple separate masking operations, thereby simplifying the overall manufacturing process while ensuring consistent alignment across all gate structures.
2Manufacturing precision
If multiple mask layers are formed for different gate structures, then manufacturing precision is improved, but manufacturing time and productivity are reduced
Solution Approach 1:
The patent merges the masking operations for multiple gate structures into a single process step. By forming the first gate structure, second gate structure, and memory gate structure simultaneously using one common mask layer, the manufacturing process eliminates multiple sequential masking steps, thereby reducing total manufacturing time and improving productivity while maintaining alignment precision.
Solution Approach 2:
The common mask layer is designed and formed in advance to simultaneously define all gate structures before any individual gate formation begins. This preliminary action of creating a comprehensive mask pattern allows all subsequent gate structures to be formed in one coordinated step, eliminating the need for multiple sequential masking operations and thus improving manufacturing efficiency.
3Ease of manufacture
If the memory gate structure covers both gate structures, then ease of manufacture is improved, but structural complexity increases
Solution Approach 1:
The patent merges the memory gate structure formation with the simultaneous formation of the first and second gate structures using a common mask layer. This approach simplifies manufacturing by reducing the number of process steps, even though the resulting structure has multiple overlapping gate components. The unified masking process makes the manufacturing easier despite the increased structural complexity.
Solution Approach 2:
The memory gate structure is positioned to cover and overlap both the first gate structure and the second gate structure, creating a nested configuration where multiple gate structures are integrated in a layered arrangement. This nesting approach allows all three gate structures to be formed in one process step while achieving the desired functional integration, simplifying manufacturing despite the complex final structure.
Data Source
AI summary
A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first gate structure disposed on the substrate, a second gate structure disposed on the substrate, and a memory gate structure disposed on the substrate and between the first gate structure and the second gate structure. The memory gate structure at least covers the first gate structure and the second gate structure. The memory gate structure includes a charge storage layer disposed on the substrate and a memory gate layer disposed on the charge storage layer.