Nonvolatile Memory Gate Structure Simultaneous Etching
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Solution Overview
Problem
The manufacturing process of split-gate memory devices is complex and time-consuming due to the need for independent deposition, planarization, and ion implantation processes for forming the select gate and memory gates.
Innovation Solution
A method where a tunnel oxide layer and first polysilicon layer are formed, followed by a gate dielectric layer and a second polysilicon layer, with all layers being patterned simultaneously through an etching process using a hard mask pattern, allowing for the formation of memory gates and a select gate with a stacked structure, thereby simplifying the process and omitting additional polysilicon layer formation and planarization steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If independent deposition, planarization, and ion implantation processes are used for forming the select gate and memory gates, then the gate structure can be formed with proper doping and alignment, but the manufacturing process becomes complex and requires unacceptably high levels of process time
Solution Approach 1:
The patent combines the formation of select gates and memory gates into a single simultaneous etching process. Multiple gates are patterned together from a common polysilicon layer, merging what were previously separate deposition and planarization steps into one unified process, thereby reducing manufacturing time while maintaining gate structure precision
Solution Approach 2:
The patent segments the gate formation process by first creating a common polysilicon layer that serves as the base for both select and memory gates, then using selective etching to define individual gate regions. This segmentation allows simultaneous formation while maintaining precise control over each gate's structure
2Reliability
If additional polysilicon layer formation and planarization steps are performed for the select gate, then proper gate structure and doping are achieved, but the manufacturing process complexity increases
Solution Approach 1:
The patent creates a universal polysilicon layer that serves as the foundation for both select gates and memory gates. This single layer performs multiple functions: it provides the conductive base for all gates, enables simultaneous patterning, and eliminates the need for separate polysilicon deposition steps for select gates, thereby reducing process complexity while maintaining structure reliability
Solution Approach 2:
The patent performs preliminary formation of the polysilicon layer and gate dielectric structure before final gate patterning. By preparing the common structural foundation in advance, the subsequent etching step can simultaneously define all gates without requiring additional layer formation or planarization, reducing both complexity and process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process time by allowing the simultaneous formation of memory gates and select gates, enabling identical bias voltage application and improved inhibit bias characteristics for nonvolatile memory devices.
Implementation Method 1
a tunneling oxide layer is formed on a substrate
Implementation Method 2
patterning the first polysilicon layer may include performing a chemical-dependent etch process
Implementation Method 3
patterning the first polysilicon layer may include performing an isotropic etching process
Data Source
AI summary
A method of manufacturing a gate structure for a nonvolatile memory device is disclosed. A tunneling oxide layer is formed on a substrate, and then a first polysilicon layer, a gate dielectric layer, a second polysilicon layer and a hard mask pattern are sequentially formed on the tunneling oxide layer. Then, the second polysilicon layer, the gate dielectric layer, and the first polysilicon layer are patterned through an etching process using the hard mask pattern to form stacked memory gates on the tunnel oxide layer, each including a floating gate, a gate dielectric layer pattern and a control gate on the tunneling oxide layer, and a select gate provided between the memory gates on the tunneling oxide layer.