Nonvolatile Memory Device Leakage Current Reduction

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Solution Overview

Problem

In three-dimensional semiconductor memory devices, abnormal disturbances occur due to leakage current at the common source line junction during programming operations, affecting the integrity of data storage.

Innovation Solution

A programming method for nonvolatile memory devices involves applying a negative voltage to a ground select line, with the absolute value controlled to be lower than the ground voltage, and a source line voltage higher than the ground voltage but lower than the power supply voltage, to reduce leakage current and prevent abnormal disturbances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a three-dimensional array structure is used to increase integration density, then the integration density is improved, but leakage current is generated at the common source line junction causing abnormal disturbance

Engineering Contradiction:
Improveintegration densityVSAvoidleakage current
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent applies parameter changes by modifying the voltage levels applied to the ground select line during programming operations. Specifically, a negative voltage (lower than ground voltage) is applied to the ground select line to counteract the leakage current generated at the common source line junction in three-dimensional array structures, thereby preventing abnormal disturbance while maintaining high integration density

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If negative voltage is applied to ground select line to reduce leakage current, then the harmful leakage current is reduced, but additional voltage control complexity is introduced

Engineering Contradiction:
Improveleakage currentVSAvoidvoltage control complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent uses the ground select line as an intermediary element to control and mitigate leakage current. By applying a negative voltage to this existing select line (rather than introducing a completely new control mechanism), the patent reduces leakage current while utilizing the existing voltage control infrastructure, thus limiting the increase in overall device complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-generated harmful factors

If absolute value of negative voltage is controlled to be equal to power supply voltage, then leakage current is effectively minimized, but voltage generation complexity increases

Engineering Contradiction:
Improveleakage currentVSAvoidvoltage generation complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent specifies that the absolute value of the negative voltage applied to the ground select line should be equal to the power supply voltage. This parameter optimization effectively minimizes leakage current by creating a symmetric voltage condition that counteracts the leakage mechanism, while the voltage generation circuit can utilize existing power supply infrastructure to produce the required negative voltage

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9595333B2Nonvolatile memory device and programming method thereof
Publication Date: 2017.03.14 SAMSUNG ELECTRONICS CO LTD
  • US9595333B2 patent drawing
  • US9595333B2 patent drawing
  • US9595333B2 patent drawing

AI summary

According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the horizontal semiconductor layer. According to example embodiments, a programming method of the nonvolatile memory device includes setting up bitlines corresponding the cell strings, setting up a plurality of string select lines connected to the cell strings, and applying a negative voltage lower to a ground select line. The ground select line is connected to a plurality of ground select transistors between the memory cells and the semiconductor layer. The string select lines extend in a direction intersecting the bitlines. The negative voltage is lower than a ground voltage.