Nonvolatile Memory Package With Hidden DQS Training
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Solution Overview
Problem
Existing nonvolatile memory packages do not perform hidden training between a buffer chip and memory chips, leading to unmatched DQS oscillator training issues after power supply, which affects data transfer efficiency.
Innovation Solution
Implementing hidden read and write training between a buffer chip and memory chips using a DQS oscillator clock, enabling periodic monitoring and adjustment of phase differences to improve sampler timing margins and data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hidden training is not performed between buffer chip and memory chips, then device complexity is reduced, but data transfer efficiency deteriorates due to unmatched DQS oscillator training
Solution Approach 1:
The patent performs hidden read training and hidden write training between the buffer chip and memory chips during the initial power-on phase, before normal data transfer operations begin. This preliminary training aligns the DQS oscillator phases and establishes optimal timing margins, ensuring high data transfer efficiency from the start without requiring complex real-time adjustments during operation.
Solution Approach 2:
The buffer chip autonomously performs hidden training operations with the memory chips using its internal DQS oscillator without requiring external controller intervention. The buffer chip self-adjusts timing parameters and phase alignments, reducing the need for complex controller-mediated training sequences and simplifying the overall system operation while maintaining high data transfer efficiency.
2Reliability
If DQS oscillator enable operation is performed periodically, then sampler timing margins are improved, but energy consumption increases
Solution Approach 1:
The buffer chip performs DQS oscillator enable operations periodically rather than continuously, specifically during hidden training phases. This periodic activation maintains sampler timing margins and ensures reliable data sampling while minimizing energy consumption by keeping the oscillator disabled during normal data transfer operations when timing alignment is already established.
3Device complexity
If hidden training is implemented without master/controller clock, then device complexity is reduced, but measurement precision of timing parameters deteriorates
Solution Approach 1:
The buffer chip acts as an intermediary between the memory chips and the controller, performing hidden training operations using its own internal DQS oscillator. This intermediary approach eliminates the need for complex master clock coordination while maintaining timing precision, as the buffer chip's oscillator serves as a stable reference for phase alignment and timing measurements during training operations.
Data Source
AI summary
A storage device includes a plurality of memory chips, a buffer chip connected to the plurality of memory chips, and a controller connected to the buffer chip. The buffer chip is configured to periodically receive a first command from the controller, and perform a DQS oscillator enable operation in response to the first command. At least one memory chip among the plurality of memory chips and the buffer chip are configured to perform write training or read training when the DQS oscillator enable operation is performed.