Non-volatile Memory Isolation Structures for Channel Length
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nitride-based flash memory experiences the second bit effect and program disturbance due to reduced channel length and increased proximity of memory devices, affecting operation window and device performance.
Innovation Solution
The non-volatile memory design includes a substrate with a gate structure, doped regions, and isolation structures, where the doped regions are formed between or surround the isolation structures, and the spacer acts as a buffer during doping, preventing dopant diffusion under the charge storage structure, thus maintaining channel length and reducing program disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel length is reduced to decrease memory size, then the memory footprint is reduced, but the second bit effect worsens
Solution Approach 1:
The patent divides the memory structure into isolated units by introducing isolation structures (trenches filled with insulating material) between adjacent memory devices. This segmentation physically separates the devices, preventing the second bit effect while allowing the channel length to be reduced for smaller memory footprint.
Solution Approach 2:
The patent introduces an intermediary isolation structure (trench with insulating material) between the adjacent memory devices. This intermediary element acts as a barrier that blocks the harmful interaction (second bit effect) between the left and right bits, allowing the devices to be placed closer together.
2Productivity
If the distance between devices is shortened to increase memory density, then the memory capacity per area is improved, but program disturbance occurs
Solution Approach 1:
The isolation structures segment the memory array into independent units, preventing program disturbance from propagating to adjacent devices. This allows higher memory density through shorter device spacing while maintaining operational integrity through the isolating trenches.
Solution Approach 2:
The isolation structures serve as intermediary barriers between adjacent memory devices. During programming operations, these intermediaries block the disturbance effects, allowing devices to be positioned closer together for increased density without suffering from program disturbance.
3Length of moving object
If the channel length is reduced to scale down memory, then the device dimensions are reduced, but the operation window decreases
Solution Approach 1:
By segmenting the memory devices with isolation structures, the patent enables shorter channel lengths while maintaining adequate electrical isolation. This prevents the degradation of operation window that would normally occur with reduced channel length, as the isolation structures prevent harmful interactions that would otherwise require longer channels to avoid.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents the second bit effect and program disturbance, maintaining a larger operation window and improving memory device performance by maintaining channel length and reducing program disturbance during programming.
Implementation Method 1
preventing dopant diffusion under the charge storage structure
Implementation Method 2
the isolation structures are disposed in the substrate at two sides of the gate structure respectively
Data Source
AI summary
A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.