Nonvolatile Memory Package for JEDEC–ONFI Compatibility
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Solution Overview
Problem
Existing memory packages and storage devices face challenges in efficiently integrating memory chips and buffer chips due to protocol incompatibilities between different interface protocols, such as JEDEC and ONFI, limiting interoperability and flexibility in data storage solutions.
Innovation Solution
A nonvolatile memory package and storage device incorporating an interface chip with bidirectional command address (CA) and chip enable (CE) pins that support both legacy and new protocols, enabling protocol conversion and compatibility through a protocol converter, allowing communication using JEDEC or ONFI standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an interface chip supports both legacy JEDEC and new ONFI protocols, then protocol compatibility and interoperability are improved, but device complexity increases due to the need for protocol conversion circuits
Solution Approach 1:
The interface chip is designed to support multiple interface protocols (JEDEC and ONFI) simultaneously, making it universal and adaptable to different memory chip types. This allows a single interface chip to handle both legacy and new protocol requirements, improving protocol compatibility without requiring separate interface chips for each protocol type.
Solution Approach 2:
A protocol converter is introduced as an intermediary component between the controller and memory chips with different protocols. The protocol converter translates and converts signals between JEDEC and ONFI protocols, enabling communication between controllers using one protocol and memory chips using another protocol, thus resolving the compatibility issue.
2Adaptability or versatility
If bidirectional CA and CE pins are used for protocol conversion, then interoperability between different memory generations is improved, but the difficulty of detecting and measuring protocol states increases
Solution Approach 1:
The interface chip incorporates feedback mechanisms to detect the operational state of bidirectional CA and CE pins. By monitoring the voltage levels and signal directions on these pins, the interface chip can determine whether it is operating in JEDEC or ONFI mode, and automatically adjust its behavior accordingly, simplifying protocol state detection.
Solution Approach 2:
The interface chip performs self-identification and self-configuration based on the detected protocol state. When the bidirectional CA and CE pins are detected to be in a specific state, the interface chip automatically configures its internal circuitry to match the required protocol, eliminating the need for external intervention or complex manual detection procedures.
Data Source
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AI summary
A storage device (1) includes at least one nonvolatile memory device (13), a controller (11) configured to control the at least one nonvolatile memory device (13), and an interface chip (12) connected to the controller (11), wherein the interface chip (12) includes a first interface circuit (12-1) configured to communicate with the controller (11) according to a first interface protocol, a second interface circuit (12-2) configured to communicate with the at least one nonvolatile memory device (13) according to a second interface protocol, and a protocol converter (12-3) configured to convert the first interface protocol to the second interface protocol or to convert the second interface protocol to the first interface protocol.