Nonvolatile Memory Page Buffer Using Static and Dynamic Latches
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in reducing size and power consumption, particularly in the design of page buffers and latch circuits, which are essential for efficient data storage and retrieval.
Innovation Solution
The implementation of a nonvolatile memory device that incorporates a static latch and dynamic latches with a shared floating node, where data is transferred and stored using write and read transistors, and a storage capacitor, allowing for reduced size and improved power efficiency through optimized transistor configurations and refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic latches are used in page buffer design, then power consumption is reduced, but device size is increased due to additional refresh circuitry
Solution Approach 1:
The patent merges the static latch and dynamic latch into a unified structure where the static latch serves as the data storage element and the dynamic latch serves as the transfer buffer. This integration allows the circuit to benefit from both static latch stability and dynamic latch power efficiency during active operations, while sharing common circuit elements like bit line connections and control logic to minimize area overhead
Solution Approach 2:
The patent implements a hybrid latch system that dynamically switches between static and dynamic latch modes based on operational requirements. During data input and processing phases, the dynamic latch is activated for low-power operation, while during data retention phases, the static latch maintains data stability. This dynamic operation allows the system to optimize power consumption without requiring full refresh circuitry for the entire page buffer
2Area of stationary object
If latch size is reduced to decrease device area, then device size is reduced, but power consumption increases due to higher switching activity
Solution Approach 1:
The patent segments the latch circuit into distinct functional blocks: a static latch for data storage, a dynamic latch for data transfer, and associated control circuitry. This segmentation allows each component to be optimized independently - the static latch uses minimal transistors for storage while the dynamic latch uses efficient transfer paths, reducing total area while maintaining low power consumption through specialized design of each segment
Solution Approach 2:
The patent applies different design qualities to different parts of the latch circuit. The static latch portion uses high-stability design with stronger transistor sizing for data retention, while the dynamic latch portion uses high-speed, low-power design with optimized switching characteristics. This local differentiation allows the overall circuit to achieve both area reduction and power efficiency by matching design characteristics to functional requirements
Data Source
AI summary
A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches.