Nonvolatile Memory Device With Localized Impurity Concentration
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in miniaturization due to increasing costs and physical limitations, such as withstand voltage issues, which hinder further integration and efficiency, especially when trying to reduce dimensions and maintain device operation.
Innovation Solution
A nonvolatile semiconductor memory device is designed with a configuration of memory strings and select transistors, featuring a U-shaped semiconductor layer with columnar portions, a charge storage layer, and conductive layers, where the effective impurity concentration of the second semiconductor layer is less than that of the first, optimizing the structure for improved integration and reduced parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the columnar semiconductor length is increased to achieve further integration, then the degree of integration is improved, but the cell current decreases and parasitic resistance increases
Solution Approach 1:
The patent applies local quality by creating a U-shaped semiconductor layer with different impurity concentrations in different regions. The first semiconductor layer (columnar portions) has a first impurity concentration optimized for memory cell operation, while the second semiconductor layer (joining portion) has a second impurity concentration optimized for current conduction. This localized optimization allows the long columnar structure to maintain both high integration and sufficient cell current by compensating for parasitic resistance through the lower-resistance joining portion.
2Productivity
If the columnar semiconductor length is increased to achieve further integration, then the degree of integration is improved, but parasitic resistance increases
Solution Approach 1:
The patent introduces a second semiconductor layer with a different impurity concentration specifically at the joining portion to locally compensate for the parasitic resistance accumulated along the extended columnar path. This localized modification reduces the harmful effect of parasitic resistance without requiring shortening of the columnar portions that would reduce integration density.
3Quantity of substance
If miniaturization is pursued to increase storage capacity, then the storage capacity is improved, but withstand voltage limitations and operational reliability deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking, where memory cells are arranged in multiple layers along the columnar semiconductor structure. This dimensional change allows storage capacity to increase vertically rather than requiring further miniaturization of individual cell dimensions, thereby maintaining withstand voltage characteristics while achieving higher storage capacity through increased cell count in the vertical direction.
Data Source
AI summary
Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer.