Nonvolatile Memory MAC Operations via Weight Storage
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Solution Overview
Problem
Neural networks require efficient semiconductor devices capable of performing a large number of multiplication and accumulation (MAC) operations, which existing technologies have not adequately addressed.
Innovation Solution
A nonvolatile memory device with a memory cell array storing weights and controlled by input signals, and a computation output circuit generating a signal corresponding to the inner product of input and weight vectors, utilizing a flash memory device to perform MAC operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor devices are used for neural network computations, then general-purpose computing functions are maintained, but the device cannot efficiently perform a large number of MAC operations required for neural networks
Solution Approach 1:
The nonvolatile memory device is designed to perform both traditional memory functions (storing data) and computational functions (MAC operations). The memory cell array can store weights, and when controlled by input signals, it performs multiplication and accumulation operations directly, eliminating the need for separate dedicated neural network processing units while maintaining general-purpose computing capabilities.
Solution Approach 2:
The patent merges the memory function and computation function into a single device. The memory cell array serves dual purposes: storing data during normal operation and performing MAC operations when configured with appropriate input signals and computation output circuits. This integration resolves the contradiction by combining previously separate functions into one versatile device.
2Productivity
If a dedicated neural network processing device is created to perform MAC operations efficiently, then computational performance for neural networks is improved, but the device complexity increases
Solution Approach 1:
The memory device performs computation using its own existing structure without requiring external processing units. The memory cell array inherently performs multiplication through its electrical characteristics when controlled by input signals, and the computation output circuit extracts the inner product result. This self-service approach enables MAC operations without adding complex external computation hardware.
Solution Approach 2:
The same memory cell array structure serves both as storage and computation unit. No separate dedicated neural network processing hardware is needed because the memory device itself can perform MAC operations when properly controlled, thereby improving computational performance without increasing overall device complexity.
3Device complexity
If existing memory devices are used for both storage and computation, then device simplicity is maintained, but the computational precision and efficiency for neural network operations are insufficient
Solution Approach 1:
The device is segmented into distinct functional components with specialized roles: the memory cell array for storing weights and performing multiplication operations, the bit line for signal transmission, and the computation output circuit for generating the inner product result. This segmentation allows each component to be optimized for its specific function, improving computational precision while maintaining overall device simplicity.
Solution Approach 2:
The patent replaces traditional computational mechanisms with electrical field-based operations in the memory device. The multiplication operation is performed through the electrical characteristics of the memory cells when controlled by input signals, and the accumulation is achieved through current summation on the bit line. This substitution of computational mechanics with electrical field operations enhances computation accuracy while keeping the device structure simple.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory elements configured to store a plurality of weights and to be controlled according to a plurality of input signals respectively and a bit line coupled to the plurality of nonvolatile memory elements; and a computation output circuit configured to generate a computation signal corresponding to an inner product between an input vector corresponding to the plurality of input signals and a weight vector corresponding to the plurality of weights.