Non-volatile Memory Metal Gate Height Control
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Solution Overview
Problem
The insufficient height of metal gate structures in flash memory regions due to simultaneous fabrication with logic device regions leads to decreased operating performance and potential failure of flash memory devices.
Innovation Solution
A non-volatile memory design with metal gate structures disposed on both sides of the charge storage structure, rather than a stacked arrangement, ensuring sufficient height and improved operating performance by maintaining consistent dummy gate heights across regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal gate structures in flash memory region and logic device region are fabricated at the same time using the same process, then manufacturing efficiency is improved, but the height of metal gate structure in flash memory region becomes insufficient
Solution Approach 1:
The patent divides the metal gate formation process into separate stages for flash memory region and logic device region. The flash memory metal gate structure is formed first, then the logic device metal gate structure is formed subsequently, allowing each region to have optimized processing parameters and preventing height interference between regions
Solution Approach 2:
The patent performs preliminary actions by forming the flash memory metal gate structure and its associated layers (tunnel dielectric layer, charge storage layer, blocking dielectric layer) before forming the logic device metal gate structure. This preliminary formation ensures that the flash memory structure has sufficient height before subsequent processing steps
2Quantity of substance
If dummy gate height in flash memory region is increased to accommodate stacked floating gate and dummy gate, then charge storage capability is improved, but dummy gate is over-removed during hard mask layer removal
Solution Approach 1:
The patent introduces an intermediary protective layer between the dummy gate and the hard mask layer removal process. This protective layer prevents the etching or polishing process from removing the dummy gate material, allowing the dummy gate to maintain its increased height necessary for charge storage functionality
Solution Approach 2:
The patent applies different structural configurations to different regions: the flash memory region has a stacked structure with floating gate and dummy gate for enhanced charge storage, while the logic device region has a conventional single gate structure. Each region's structure is optimized for its specific function
Data Source
AI summary
A non-volatile memory including a substrate, a charge storage structure, two metal gate structures, a first dielectric layer, a second dielectric layer, a first doped region and a second doped region is provided. The charge storage structure is disposed on the substrate. The metal gate structures are disposed on the substrate at two sides of the charge storage structure. The first dielectric layer is disposed between the charge storage structure and the metal gate structures. The second dielectric layer is disposed between the charge storage structure and the substrate. The first doped region and the second doped region are disposed in the substrate at sides of the metal gate structures away from the charge storage structure.