Non-volatile Memory Elements Multi-Level Cell Configuration
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Solution Overview
Problem
There is a need for improved structures and methods in fabricating non-volatile memory elements, particularly in resistive random-access memory (ReRAM) devices, to enhance data storage capabilities and efficiency.
Innovation Solution
The proposed solution involves a structure and method for fabricating non-volatile memory elements with a switching layer between two electrodes, where bit lines are coupled to the electrodes, allowing for multiple data storage levels by changing resistance states, and using materials like ruthenium, platinum, and silicon dioxide to create conductive filaments for low-resistance states and destroying them for high-resistance states, with additional configurations using phase change, ferroelectric, or magnetic tunnel junction materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional single-level memory structures are used, then the device structure is simple, but the memory density and data storage capability are limited
Solution Approach 1:
The patent implements multi-level cell (MLC) configuration by stacking multiple non-volatile memory elements vertically in a single memory location. This vertical stacking approach transitions from planar single-level storage to three-dimensional multi-level storage, enabling multiple data bits to be stored in the same footprint area by utilizing the vertical dimension. The bit line coupling structure connects multiple memory elements at different vertical levels to enable simultaneous access and multi-level data storage.
Solution Approach 2:
The patent employs a nested configuration where multiple non-volatile memory elements are arranged in a hierarchical structure with shared bit lines. The first and second non-volatile memory elements are nested within the same memory cell structure, sharing common bit line connections while maintaining independent switching layers. This nesting approach maximizes space utilization and enables multi-level storage without proportionally increasing device footprint.
2Quantity of substance
If more memory elements are added to increase storage capacity, then the data storage capability improves, but the fabrication complexity and cost increase
Solution Approach 1:
The patent designs a universal bit line coupling structure that serves multiple functions: it connects multiple non-volatile memory elements, enables selective access to individual elements, and supports multi-level data storage operations. The switching layers use similar dielectric materials and filament formation mechanisms across all memory elements, allowing standardized fabrication processes to be applied universally throughout the array, thereby reducing per-bit fabrication complexity despite increased storage capacity.
3Loss of information
If resistance states are changed to store data, then data storage is achieved, but energy is consumed during write operations
Solution Approach 1:
The patent utilizes the resistive switching phenomenon where high current density applied during write operations temporarily forms conductive filaments through the dielectric switching layer. These filaments create low-resistance states for data storage. The same dielectric material that initially resists current flow (harms) ultimately enables non-volatile data retention through controlled filament formation (benefit). The energy consumed during write operations transforms the dielectric material's resistance properties to create stable data-storing conductive paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables multi-level data storage in a smaller area, improving memory density and reducing costs per bit, while also simplifying the fabrication process and allowing for efficient programming and reset operations.
Implementation Method 1
The dielectric material can be modified by applying a bias voltage sufficient to create one or more filaments as conductive paths bridging across the thickness of the dielectric material
Implementation Method 2
The filaments of the resistive random-access memory element are destroyed, also by the application of a bias voltage, to write the high-resistance state
Data Source
AI summary
Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. A first non-volatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A second non-volatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the second electrode of the first non-volatile memory element.