Nonvolatile Memory Multilevel Cell Programming Buffer Optimization
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Solution Overview
Problem
In NAND flash memory systems, particularly in three-dimensional nonvolatile memory, the increasing memory capacity requires a reduction in the write buffer size of the memory controller to avoid inter-cell interference and bit error rate biases, while maintaining data reliability and reducing the cost of the memory controller.
Innovation Solution
A memory system with a nonvolatile memory that uses 16 threshold regions to store 4-bit data, where the memory controller executes two programs to write data, optimizing the number of boundaries between threshold regions to minimize inter-cell interference and bit error rates, and reduces the write buffer capacity by discarding redundant data after each program stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 4-bit data is written simultaneously to multiple memory cells to avoid inter-cell interference, then data reliability is improved, but the write buffer capacity requirement increases
Solution Approach 1:
The patent divides the writing process into multiple stages, where data is written to different memory cells in sequential batches rather than all simultaneously. The memory controller writes data to a first set of memory cells, then to a second set, and finally rewrites to the first set, thereby segmenting the write operations to reduce peak buffer requirements while maintaining reliability through multiple write passes
Solution Approach 2:
The patent performs preliminary writing operations to a first set of memory cells before writing to adjacent cells. Data is prepared and written to initial target cells, then subsequent writes to adjacent cells are performed, with final rewriting to ensure data integrity. This preliminary action allows the system to manage buffer usage more efficiently by staging write operations
2Ease of manufacture
If write buffer capacity is reduced to lower memory controller cost, then manufacturing cost is improved, but inter-cell interference increases
Solution Approach 1:
By segmenting the write operations into multiple stages targeting different memory cell sets sequentially, the patent reduces the amount of data that must be held in the write buffer simultaneously, thereby reducing buffer capacity requirements and manufacturing cost while minimizing inter-cell interference through temporal separation of write operations
Solution Approach 2:
The patent employs periodic write operations where data is written to different sets of memory cells in alternating cycles. The memory controller performs write operations to a first set of memory cells, then to a second set, and repeats this pattern, creating a periodic action that allows smaller buffer capacity while maintaining data reliability and reducing interference
3Quantity of substance
If data is written in a dividing manner to reduce write buffer amount, then write buffer capacity is reduced, but bit error rate becomes biased
Solution Approach 1:
The patent merges multiple write operations into a comprehensive writing process that includes initial writes to a first set of memory cells, writes to a second set of memory cells, and final rewriting to the first set. This merging of operations ensures all bits are written with consistent parameters, eliminating bit error rate bias while still reducing write buffer capacity requirements through the staged approach
Solution Approach 2:
The patent incorporates feedback mechanisms where the memory controller monitors the writing process and adjusts subsequent operations to ensure uniform bit error rates. The rewriting operation to the first set of memory cells serves as a feedback-based correction step that ensures data integrity and uniform error characteristics across all bits
Data Source
AI summary
A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.