Nonvolatile Memory Multilevel Data Storage Activation

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Solution Overview

Problem

Current data processing systems face challenges in achieving high-speed processing, large capacitance, reduced size, power consumption, and cost, particularly in increasing the storage capacity of main memory devices when activated.

Innovation Solution

A data processing system incorporating an arithmetic processing device and a nonvolatile memory device with memory cells that store s-bit data when inactive and t-bit data when activated, utilizing transistors with metal oxides in the channel formation region, allowing for increased storage capacity and efficient data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional memory devices (DRAM, SRAM, flash memory) are used in data processing systems, then high-speed processing and data storage are achieved, but the storage capacity of main memory devices cannot be easily increased when the system is activated

Engineering Contradiction:
Improvedata processing speedVSAvoidstorage capacity expandability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The memory device dynamically changes its storage capacity from s-bit to t-bit (where t > s) upon activation. The control circuit detects the activated state and switches the memory cells from storing s-bit data to storing t-bit data, enabling adaptive expansion of storage capacity based on system activation status.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the data storage parameter (number of bits per memory cell) based on the activation state. When activated, the memory device transitions from storing s-bit data to storing t-bit data per cell, effectively increasing storage capacity through parameter transformation rather than physical expansion.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If larger storage capacity is implemented in main memory devices, then data processing capability is improved, but device size, power consumption, and cost increase

Engineering Contradiction:
Improvestorage capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The memory device provides dynamic storage capacity adjustment, storing s-bit data when inactive and t-bit data when activated. This allows the system to have large storage capacity only when needed, reducing power consumption during idle states while maintaining high productivity when the system is active.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention implements partial capacity expansion - memory cells store t-bit data (excessive capacity) only when the system is activated, rather than always maintaining full capacity. This partial action approach provides high storage capacity when needed without the continuous power consumption penalty of maintaining that capacity at all times.

Inventive Principle:
Principle #16Partial or excessive action

3Adaptability or versatility

If multilevel data storage (t-bit where t>1) is implemented in nonvolatile memory devices, then storage capacity is increased when activated, but device complexity increases

Engineering Contradiction:
Improvestorage capacityVSAvoidmemory cell structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The same memory cell structure serves multiple functions: it stores s-bit data during inactive periods and t-bit data during activated periods. The control circuit enables this memory cell to perform both storage modes without requiring separate physical structures, reducing overall device complexity while achieving multilevel storage capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The memory device dynamically switches between s-bit and t-bit storage modes using the same physical memory cell structure. The control circuit adjusts the operating parameters to enable the memory cell to store different bit depths based on activation state, achieving multilevel storage without permanently increasing structural complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12014175B2Data processing system and operation method of data processing system
Publication Date: 2024.06.18 SEMICON ENERGY LAB CO LTD
  • US12014175B2 patent drawing
  • US12014175B2 patent drawing
  • US12014175B2 patent drawing

AI summary

To provide a data processing system that includes a nonvolatile memory device capable of storing multilevel data and enables increasing storage capacity of a main memory device when the data processing system is activated. The data processing system includes an arithmetic processing device, a main memory device, and a nonvolatile memory device. The main memory device includes a volatile memory device, and the nonvolatile memory device is configured to store multilevel data in one memory cell. When the data processing system is deactivated, the nonvolatile memory device stores binary data, whereby the stored data can be held for a long time. Upon activation, the nonvolatile memory device stores multilevel data, whereby increasing storage capacity. When the storage capacity is increased, a free space is generated in the nonvolatile memory device, which can be used as a part of the main memory device of the data processing system.