Nonvolatile Memory Near-Far Cell Read Disturbance

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Solution Overview

Problem

Next-generation nonvolatile memory apparatuses face challenges in balancing high operation speed with reduced read disturbance and power consumption, particularly due to the distance-dependent voltage and current distribution across near and far areas within cell arrays, which affects data retention and access efficiency.

Innovation Solution

The nonvolatile memory apparatus employs a dual read operation strategy, with a first read operation performed for a longer duration on memory cells in the near area and a second read operation on memory cells in the far area, using scrambled address signals and distinct read pulse signals to optimize voltage and current application, thereby minimizing read disturbance and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single read operation is performed on all memory cells, then the read operation is simple and fast, but read disturbance occurs in near-area cells and power consumption increases

Engineering Contradiction:
Improveread operation speedVSAvoidread disturbance
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The memory array is divided into near-area and far-area cell groups based on their distance from the read circuit. Different read operations are applied to these segments: the first read operation with longer pulse width for near-area cells and the second read operation with shorter pulse width for far-area cells, thereby reducing read disturbance while maintaining speed

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different read operation parameters are applied locally to different regions of the memory array. The near-area cells receive the first read operation with longer pulse width to ensure complete read, while far-area cells receive the second read operation with shorter pulse width, optimizing each region according to its specific characteristics

Inventive Principle:
Principle #3Local quality

2Reliability

If the first read operation with longer duration is performed on all memory cells, then data retention is improved, but power consumption increases

Engineering Contradiction:
Improvedata retentionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The memory cells are segmented into near-area and far-area groups, and the first read operation with longer duration is applied selectively only to near-area cells where it is most needed for data retention, while far-area cells use the shorter second read operation, thereby reducing overall power consumption while maintaining reliability where critical

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The longer first read operation is applied partially only to near-area cells rather than all cells. This partial application provides excessive read duration for near-area cells to ensure data retention, while avoiding the unnecessary energy consumption that would result from applying it to all cells uniformly

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If more cell arrays perform the first read operation, then data retention is improved, but the number of active cell arrays increases reducing system efficiency

Engineering Contradiction:
Improvedata retentionVSAvoidsystem efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The first read operation is applied locally only to near-area cells in each cell array rather than uniformly across all cell arrays. This localized approach ensures data retention for near-area cells while minimizing the number of active cell arrays, thereby improving system efficiency

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10998043B2Nonvolatile memory apparatus and memory system using the same
Publication Date: 2021.05.04 MIMIRIP LLC
  • US10998043B2 patent drawing
  • US10998043B2 patent drawing
  • US10998043B2 patent drawing

AI summary

A nonvolatile memory apparatus includes a plurality of cell arrays, each including a near area and a far area. A plurality of memory cells are included in the near area, and a plurality of memory cells are included in the far area. When a memory cell of the plurality of memory cells, included in a near area of at least one cell array, among the plurality of cell arrays, is selected, based on an address signal, the nonvolatile memory apparatus selects memory cells included in far areas of the remaining cell arrays based on the address signal. The nonvolatile memory apparatus performs a first read operation on the selected memory cell of the at least one cell array, and performs a second read operation on the selected memory cells of the remaining cell arrays.