Nonvolatile Memory Device With Non-Power-of-Two Capacity
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Solution Overview
Problem
Current nonvolatile memory systems face challenges in increasing memory capacity without scaling down process technology, as larger components do not fit within standard packages due to physical constraints, and scaling down technology is a costly investment.
Innovation Solution
A nonvolatile memory device with a non-power of two capacity is designed, featuring a plurality of blocks divided into pages along two dimensions, with a proportional number of row decoders for read operations, and a controller that includes a map table to handle invalid physical addresses, allowing for efficient memory management and capacity expansion without changing package sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is doubled for every generation, then memory capacity increases, but physical size increases causing components to not fit within standard packages
Solution Approach 1:
The patent applies dimensionality change by organizing memory cells in a three-dimensional stacked architecture rather than a traditional planar two-dimensional layout. Multiple layers of memory cells are stacked vertically, allowing memory capacity to increase in the vertical dimension while maintaining a compact footprint that fits within standard package dimensions. This enables higher density without increasing the horizontal package area.
Solution Approach 2:
The patent implements nesting by placing multiple memory cell layers within a single package footprint, similar to nested dolls. Each layer is contained within the same horizontal boundary, with layers stacked one inside another vertically. This nested structure allows the total memory capacity to exceed what would be possible in a single layer while remaining within the same package constraints.
2Quantity of substance
If process technology is scaled down to increase memory capacity, then memory capacity increases, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies parameter changes by modifying the architectural configuration of the memory device rather than changing the process technology parameters. Instead of scaling down transistor dimensions through more expensive fabrication processes, the invention changes the spatial arrangement parameter by stacking memory layers vertically. This architectural parameter change achieves higher capacity while using existing, cost-effective manufacturing processes.
3Ease of operation
If standard packages are used to maintain compatibility, then ease of operation is improved, but memory capacity is limited by physical constraints
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension for capacity expansion while maintaining the horizontal footprint compatible with standard packages. The memory device fits within conventional package dimensions, ensuring compatibility with existing PCB layouts and mounting infrastructure, while achieving higher capacity through vertical stacking of memory layers.
Data Source
AI summary
A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device.