Nonvolatile Memory On-Chip Encoding Foggy-Fine Programming
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Solution Overview
Problem
Existing non-volatile memory devices, such as NAND structures, face challenges in efficiently programming memory cells without disturbing previously programmed cells, requiring multiple program operations and significant data storage capacity, which leads to resource overhead and bus traffic.
Innovation Solution
The implementation of foggy-fine programming, where memory cells are initially programmed to approximate 'foggy' distributions followed by more accurate 'fine' distributions, with on-chip encoding and decoding using parity data to recover original data, reducing program disturb effects and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If programming occurs in multiple program operations to mitigate program disturb effects, then program disturb effects are reduced, but significant data storage capacity and overhead are required to maintain data between operations
Solution Approach 1:
The programming operation is divided into two distinct stages: foggy programming that creates an intermediate state, and fine programming that achieves the final state. This segmentation allows the system to mitigate program disturb effects by performing fine programming only on cells that need adjustment, rather than programming all cells to final state immediately.
Solution Approach 2:
Foggy programming is performed as a preliminary action to bring memory cells close to their target state before fine programming. This preliminary programming reduces the magnitude of subsequent programming operations needed during fine programming, thereby reducing program disturb effects on neighboring cells while maintaining data integrity.
2Reliability
If multiple program operations are used to program memory cells, then program disturb effects are mitigated, but significant bus traffic and resource overhead occur due to data movement between components
Solution Approach 1:
The patent extracts and stores only the necessary parity data on-chip in SLC memory cells, rather than maintaining complete data copies in external buffers. This extraction of essential error correction information reduces the amount of data that needs to be moved over the bus between memory operations.
Solution Approach 2:
The memory device performs self-service by incorporating on-chip encoding and decoding circuits that operate autonomously during foggy-fine programming. The system can recover and correct data using stored parity data without requiring external controller intervention, reducing bus traffic and resource overhead.
3Quantity of substance
If on-chip encoding with parity data is implemented, then data recovery is enabled without safe copies, but additional on-chip circuits are required
Solution Approach 1:
The patent merges the encoding function with the existing memory structure by implementing XOR circuits that operate within the memory device itself. The parity data is stored in SLC memory cells that are integrated into the same device, combining storage and error correction functionality in a unified architecture.
Solution Approach 2:
The SLC memory cells serve multiple functions: they store both user data and parity data, and can be used for both foggy programming and fine programming operations. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall device complexity.
Data Source
AI summary
A non-volatile storage apparatus includes a plurality of non-volatile memory cells formed on a memory die, each non-volatile memory cell configured to hold a plurality of bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data.