Non-volatile Memory Page Buffer with On-Chip Valley Search Read Method
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Solution Overview
Problem
Non-volatile memory devices face challenges in accurately reading data from memory cells due to errors caused by degradation, leading to unreliable data retrieval, especially in multi-level cell systems where precise voltage thresholds are critical.
Innovation Solution
The implementation of a non-volatile memory device with a page buffer and control logic that performs multiple sensing operations to identify the state of memory cells, selecting optimal data by comparing results from different read signals and voltages, thereby reducing error bits and improving data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple sensing operations are performed to accurately identify memory cell states, then data reliability is improved, but device complexity and read time increase
Solution Approach 1:
The page buffer is divided into multiple latch sets (first latch set, second latch set, third latch set) that can independently store results from different sensing operations. This segmentation allows parallel processing of multiple read operations without requiring a single complex buffer, thereby improving data reliability through multiple sensing while managing device complexity through modular architecture.
Solution Approach 2:
The control logic performs preliminary comparison and selection of optimal read signals before final data output. By pre-comparing results from different latch sets and selecting the most reliable data before output, the system ensures high data reliability without requiring all sensing operations to complete fully, thus managing read time and complexity.
2Reliability
If multiple sensing operations are performed to reduce error bits, then data reliability is improved, but read time increases
Solution Approach 1:
The system performs sensing operations periodically with different read signals (first read signals, second read signals, third read signals) at different develop timings. By using periodic sensing with optimized timing intervals, the system reduces error bits through multiple measurements while controlling overall read time through efficient timing management.
Solution Approach 2:
The control logic performs preliminary comparison and selection of optimal read signals before final data output. By pre-comparing results from different latch sets and selecting the most reliable data before output, the system ensures high data reliability without requiring all sensing operations to complete fully, thus managing read time and complexity.
3Reliability
If optimal data is selected by comparing sensing results, then data reliability is improved, but device complexity increases
Solution Approach 1:
The control logic automatically compares sensing results from different latch sets and autonomously selects optimal data without external intervention. The page buffer and control logic work together to self-manage the data selection process, improving data reliability through automatic error detection and correction while managing complexity through integrated control rather than external complex processing.
Data Source
AI summary
A non-volatile memory device includes a page buffer and a control logic. The page buffer includes a plurality of latch sets that latches first results of a plurality of first read operations according to a plurality of read signals. The first read operations identify a single page datum from among a plurality of page data of selected memory cells included in a plurality of memory cells. The control logic selects a portion of the read signals by comparing the first results of the first read operations, and resets remaining read signals that are not selected. The page buffer stores second results of second read operations according to the selected read signals, and third results of third read operations according to the reset remaining read signals.