Nonvolatile Memory Page Buffer Circuitry for Fast Data State Sensing

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Solution Overview

Problem

Current nonvolatile memory devices face challenges in improving the speed and reliability of reading data from memory cells, particularly in efficiently determining the states of data stored in these devices.

Innovation Solution

The proposed solution involves a nonvolatile memory device architecture with a memory cell region and a peripheral circuit region, utilizing first and second metal pads for vertical connection, and employing a page buffer circuitry that performs distinct sensing operations on bit lines to accurately determine the states of memory cells, including precharge voltages and inverted sensing operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional reading methods are used in nonvolatile memory devices, then the structure remains simple, but the speed and reliability of determining data states in memory cells is insufficient

Engineering Contradiction:

Improvespeed of determining data statesVSAvoidcomplexity of sensing operation structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The bit lines are divided into first bit lines and second bit lines, with corresponding first and second sensing operations performed independently. This segmentation allows parallel processing of different memory cell groups, improving the speed of determining data states while maintaining manageable circuit complexity through modular organization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a dual-sensing-dimension approach by performing both first sensing operations (direct sensing) and second sensing operations (inverted sensing) on different bit line groups. This multi-dimensional sensing strategy enhances reliability through cross-validation while achieving faster overall determination through parallel operation.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple sensing operations are performed to improve reliability, then the accuracy of data state determination increases, but the time required for check operations increases

Engineering Contradiction:

Improvereliability of data state determinationVSAvoidtime for check operations

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The first and second sensing operations are performed in parallel on different bit line groups before the final check operation. This preliminary parallel sensing reduces the total time required for reliable data state determination, as both sensing paths operate simultaneously rather than sequentially.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuous useful action by performing sensing operations on both first and second bit lines concurrently throughout the check operation. This continuous parallel sensing maximizes resource utilization and minimizes idle time, achieving high reliability without proportional time increase.

Inventive Principle:

Principle #20Continuity of useful action

3Measurement precision

If inverted sensing operations are implemented, then read errors are minimized through valley search methods, but the circuit complexity in page buffer circuitry increases

Engineering Contradiction:

Improveprecision of data state sensingVSAvoidcomplexity of page buffer circuitry

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The page buffer circuitry is segmented into first page buffers for direct sensing and second page buffers for inverted sensing. This segmentation isolates the complexity of inverted sensing operations to specific circuit modules, making the overall system more manageable while achieving enhanced measurement precision through the valley search method.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate sensing nodes and buffer circuits that facilitate the inverted sensing operation. These intermediary elements enable precise valley search detection while containing the complexity within dedicated circuit blocks, preventing it from propagating throughout the entire memory system.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11031071B2Nonvolatile memory device, operating method of nonvolatile memory device, and storage device including nonvolatile memory device

Publication Date: 2021.06.08 SAMSUNG ELECTRONICS CO LTD

AI summary

A nonvolatile memory device includes a memory cell region including first metal pads and a memory cell array, and a peripheral circuit region including second metal pads, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted. The peripheral circuit region is vertically connected to the memory cell region by the metal pads directly.