Nonvolatile Memory Page Buffer Unit for Simultaneous Program Verification
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Solution Overview
Problem
In nonvolatile memory devices, the intelligent verification operation can lead to errors due to data collisions when program verification using multiple verification voltages, causing increased program time as column scans are stopped and resumed during data input, affecting efficiency.
Innovation Solution
A nonvolatile memory device with a page buffer unit and a fail bit count unit that allows for simultaneous data input and program verification using a common verification line, enabling error correction based on fail bit counts and controlling program operations to prevent data collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If column scan is stopped and resumed during data input for intelligent verification, then data collision errors are prevented, but program time increases due to operation interruptions
Solution Approach 1:
The patent applies preliminary action by performing verification operations using a separate verification line before main data input operations begin. The verification line operates independently to check fail bits and generate verification results in advance, so that when column scan resumes or continues during data input, no data collision occurs and no interruption is needed, thus maintaining both reliability and reducing time loss
2Productivity
If simultaneous data input and program verification are performed using a common verification line, then program time is reduced, but data collision errors occur leading to verification inaccuracies
Solution Approach 1:
The patent applies segmentation by dividing the verification function into two separate pathways: a verification line for performing verification operations and generating verification results, and a common line for data input operations. This segmentation allows simultaneous operation of both functions without data collision, as each operates through its dedicated pathway, thus achieving both high productivity and reliability
3Measurement precision
If multiple verification voltages are used for intelligent verification, then error detection capability is improved, but data collision errors occur during verification operations
Solution Approach 1:
The patent introduces an intermediary verification line that mediates between the multiple verification voltages and the common line used for data input. The verification line receives verification voltages, performs verification operations, and outputs verification results through this intermediary pathway, preventing direct interaction between verification signals and data input signals that would cause data collision, thus maintaining both measurement precision and reliability
Data Source
AI summary
In a nonvolatile memory device, a cache program operation for the next data is performed in a first latch, and a verification program operation for the current data is performed using a second latch. Thus, data collision can be avoided and execution time can be reduced.