Non-Volatile Memory Page-Level Data Correction Without Block Erase

Solution Overview

Problem

Traditional flash memory devices require a full block erase operation to correct data in a single page, which slows down the process and increases the number of program/erase cycles, affecting reliability and longevity.

Innovation Solution

A non-volatile memory device that allows data correction by page without an erase operation, using a control circuit to re-program multi-level cells with higher verify voltage levels, enabling data correction within the same block without affecting other pages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a full block erase operation is performed to correct data in a single page, then data correction can be achieved, but the process speed decreases and the number of program/erase cycles increases

Engineering Contradiction:

Improvedata correction capabilityVSAvoidprocess speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the block erase operation into page-level operations. Instead of erasing the entire block to correct a single page, the system performs targeted re-programming operations only on the affected page, dividing the large-scale operation into smaller, more efficient units.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the operational parameters by using higher verify voltage levels for re-programming. By applying elevated voltage levels during the verify and re-program phases, the system can reliably correct data without requiring a full erase cycle, thus maintaining correction reliability while improving speed.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a full block erase operation is performed to correct data in a single page, then data correction can be achieved, but the number of program/erase cycles increases

Engineering Contradiction:

Improvedata correction capabilityVSAvoidmemory device longevity

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent segments the block erase operation into page-level operations. Instead of erasing the entire block to correct a single page, the system performs targeted re-programming operations only on the affected page, dividing the large-scale operation into smaller, more efficient units.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the operational parameters by using higher verify voltage levels for re-programming. By applying elevated voltage levels during the verify and re-program phases, the system can reliably correct data without requiring a full erase cycle, thus maintaining correction reliability while improving speed.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If other pages of a block remain unchanged while correcting a particular page, then data integrity is maintained, but the typical erase-all method still requires erasing and re-writing all pages

Engineering Contradiction:

Improvedata integrityVSAvoidcorrection time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the correction operation from the context of a full block erase. By isolating and targeting only the affected page for re-programming while leaving other pages untouched, the system removes the unnecessary erase-and-rewrite steps for unaffected data, significantly reducing correction time.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies local quality by using different operational approaches for different pages within the same block. Affected pages receive targeted re-programming with higher verify voltages, while unaffected pages remain unchanged, allowing each page to be treated according to its specific needs rather than applying a uniform erase-all approach.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8508990B2Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device

Publication Date: 2013.08.13 SAMSUNG ELECTRONICS CO LTD

AI summary

A non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit is configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels.