Nonvolatile Memory Logical Page Sorting for FTL Table Reduction

The patent applies preliminary action by sorting logical pages by their logical addresses before writing them to physical locations in the nonvolatile memory device. This pre-sorting operation prepares the data in advance, allowing the FTL to maintain a more compact translation table while still enabling efficient sequential writes. The sorting is performed on the logical page addresses before the actual write operation, thus preventing table bloat from unsorted address mappings.

The patent merges the sorting operation with the existing write process by integrating the logical address sorting step directly into the write workflow. Instead of treating sorting as a separate complex stage, the system combines sorting and writing into a coordinated process where logical pages are sorted by their addresses and then immediately written to the nonvolatile memory device in the sorted order. This integration reduces overall system complexity despite adding a sorting step, as the sorting operates on already-structured data and prepares it for sequential storage.

The patent applies segmentation by organizing the nonvolatile memory device into multiple blocks, each capable of storing sorted logical pages. This segmentation allows the system to maintain sorted order within each block for efficient FTL table management while enabling parallel or independent access to different blocks for random read operations. The logical address sorting is performed at the block level, creating manageable segments that balance mapping efficiency with access performance.