Nonvolatile Memory Sub-Processor for Parallel Program Verification
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Solution Overview
Problem
Existing nonvolatile memory devices require prolonged time for program operations due to sequential performance of program voltage apply and verify operations, which can be optimized for faster processing.
Innovation Solution
A memory device with a sub-processor that controls parallel execution of program-related voltage application and pass/fail check operations, alongside a main processor managing overall control, allowing simultaneous execution of these tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If program voltage apply operation and verify operation are performed sequentially, then reliability of data storage is ensured, but time required for program operation is lengthened
Solution Approach 1:
The control logic is segmented into a main processor for voltage control and a sub-processor for pass/fail check operations. This segmentation allows the verify operation to be performed in parallel with the program voltage apply operation, reducing the total time while maintaining reliability through separate dedicated control paths for each function.
Solution Approach 2:
The patent introduces a temporal dimension by enabling parallel execution of program voltage apply and verify operations through dual processor architecture. The main processor handles voltage application while the sub-processor simultaneously performs verify operations, transforming a sequential one-dimensional process into a parallel multi-dimensional execution model.
2Ease of operation
If program voltage apply operation and verify operation are performed sequentially, then control simplicity is maintained, but productivity of memory device is reduced
Solution Approach 1:
The control function is divided into two independent processors: a main processor for voltage control and a sub-processor for verify operations. This segmentation enables parallel execution, improving productivity from 100% sequential to approximately 50% parallel efficiency, while each processor maintains simple dedicated control logic.
Solution Approach 2:
The dual processor architecture provides multi-functionality where the main processor handles voltage control and the sub-processor handles verify operations. This universal design allows both functions to execute simultaneously, enhancing productivity without complicating the overall control structure as each processor has a specialized single function.
3Device complexity
If single processor controls both voltage application and verify operations, then device complexity is reduced, but time required for program operation increases
Solution Approach 1:
The control function is divided into two independent processors: a main processor for voltage control and a sub-processor for verify operations. This segmentation enables parallel execution, reducing the total time while maintaining reliability through separate dedicated control paths for each function.
Solution Approach 2:
The patent introduces a temporal dimension by enabling parallel execution of program voltage apply and verify operations through dual processor architecture. The main processor handles voltage application while the sub-processor simultaneously performs verify operations, transforming a sequential one-dimensional process into a parallel multi-dimensional execution model.
Data Source
AI summary
Provided herein is a memory device and a method of operating the same. The memory device includes memory cells coupled between a word line and bit lines, a main processor configured to control program-related voltages that are applied to the word line and the bit lines, a page buffer configured to store data sensed based on threshold voltages of the memory cells, a sensing circuit configured to perform a pass/fail check operation of comparing a sensing current corresponding to the sensed data with a reference current, and a sub-processor configured to control the page buffer and the sensing circuit to perform the pass/fail check operation in parallel with control of the program-related voltages while the main processor controls the program-related voltages.