Nonvolatile Memory Initialization via Parallel Plane Sensing
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Solution Overview
Problem
The increasing integration degree and memory capacity of nonvolatile memory devices, such as three-dimensional NAND flash memory, lead to longer initialization times and a higher probability of dump-down failures due to the need to read and verify setting data from multiple memory regions, which is inefficient and error-prone.
Innovation Solution
A method and device that perform parallel sensing and verification of write setting data across multiple memory planes, using page buffer circuits and verification circuits to store and validate read setting data, allowing for a complementary scheme to ensure data validity and reduce dump-down sequence time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration degree and memory capacity of nonvolatile memory devices are increased, then the storage capacity is improved, but the initialization time increases
Solution Approach 1:
The memory device is divided into multiple memory planes (first memory plane, second memory plane, etc.), each with its own page buffer circuit. This segmentation allows parallel sensing operations to be performed on different planes simultaneously, reducing the overall initialization time while maintaining high memory capacity.
Solution Approach 2:
The patent transitions from sequential plane-by-plane sensing to parallel multi-plane sensing by utilizing the spatial dimension of multiple memory planes. Multiple sensing operations occur simultaneously across different planes, effectively adding a temporal dimension to the initialization process and reducing total initialization time.
2Quantity of substance
If the integration degree and memory capacity of nonvolatile memory devices are increased, then the storage capacity is improved, but the probability of dump-down failures increases
Solution Approach 1:
Verification circuits perform validity verification of setting data before the dump-down operation. This preliminary verification identifies and flags potentially erroneous data in advance, allowing the system to prevent or correct dump-down failures before they occur, thereby improving reliability without reducing memory capacity.
Solution Approach 2:
The verification circuits provide feedback on the validity of setting data read from memory planes. This feedback mechanism enables the system to detect errors in setting data and take corrective actions, reducing the probability of dump-down failures while maintaining high integration度和存储容量.
3Reliability
If setting data is read and verified from multiple memory regions sequentially, then data validity is ensured, but the initialization process becomes inefficient
Solution Approach 1:
The memory system is segmented into multiple independent memory planes with dedicated page buffer circuits and verification circuits for each plane. This segmentation enables parallel sensing and verification operations across multiple planes simultaneously, maintaining data validity through comprehensive verification while dramatically improving initialization efficiency by eliminating sequential processing bottlenecks.
Solution Approach 2:
The patent merges multiple sensing operations and verification processes into a parallel execution framework where multiple memory planes are sensed and verified simultaneously. This merging of operations in the spatial domain (across multiple planes) maintains thorough data validation while improving overall initialization throughput and efficiency.
Data Source
AI summary
A method includes performing a first sensing operation to sense write setting data stored in first memory cells of a first memory plane and store first read setting data in a first page buffer circuit of the first memory plane, performing a second sensing operation to sense the write setting data stored in second memory cells of a second memory plane and store second read setting data in a second page buffer circuit of the second memory plane and performing a dump-down operation to store restored setting data corresponding to the write setting data in a buffer based on the first read setting data and the second read setting data.