3D Nonvolatile Memory Pass Transistor Arrangement
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density and efficient data retention in nonvolatile memory devices, particularly in maintaining data integrity when power is interrupted.
Innovation Solution
A nonvolatile memory device with a three-dimensional array structure, featuring first and second word lines, memory blocks, and pass transistors arranged in parallel rows, allowing for selective connection and disconnection of memory blocks and word lines to enhance data storage and retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pass transistors are arranged in conventional layouts, then device complexity is reduced, but integration density cannot be increased
Solution Approach 1:
The patent transitions from conventional two-dimensional planar arrangement of pass transistors to a three-dimensional vertical stack configuration. Multiple pass transistors are stacked vertically above each other, utilizing the third dimension (height) to increase integration density without expanding the lateral footprint. This dimensional change allows higher transistor density while maintaining manageable device complexity through standardized vertical stacking techniques.
2Quantity of substance
If memory blocks are arranged in three-dimensional arrays, then integration density is increased, but data retention efficiency deteriorates
Solution Approach 1:
The patent divides the three-dimensional memory array into multiple independently controllable memory blocks, each with its own dedicated pass transistors and word lines. This segmentation allows selective activation and retention of data in specific blocks while others remain inactive or are refreshed differently. The block-level independence enables efficient power management and data retention strategies for each segment, maintaining reliability in 3D configurations.
Solution Approach 2:
The patent introduces pass transistors as intermediary elements between the control circuitry and the memory cells in the three-dimensional array. These pass transistors act as selective gates that control data access and retention for specific memory blocks and word lines. By using pass transistors as intermediaries, the system can precisely manage power delivery and data retention in different regions of the 3D array, preventing data loss while maintaining high integration density.
3Quantity of substance
If conventional memory structures are used, then manufacturing is simpler, but integration density cannot be increased
Solution Approach 1:
The patent implements a nested structure where multiple levels of memory blocks are stacked vertically, with each level containing complete memory block functionality (cells, word lines, pass transistors). These nested memory blocks are interconnected through vertical conductive structures, creating a compact three-dimensional architecture. This nesting approach increases integration density by utilizing vertical space while employing standardized manufacturing techniques for forming stacked structures, making the complex 3D architecture manufacturable through established processes.
Data Source
AI summary
A nonvolatile memory device includes a first memory block connected to first word lines, a second memory block arranged in a direction perpendicular to the first memory block and is connected to second word lines, first pass transistors for enabling the first word lines, and second pass transistors for enabling the second word lines. The first and second pass transistors are arranged in a horizontal direction with respect to the first and second memory blocks.