Non-Volatile Memory Device Pass Transistor Architecture
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Solution Overview
Problem
Conventional NAND and NOR type flash memory devices have distinct limitations, such as fast program speed but slow reading in NAND, and fast reading but slow programming in NOR, making them unsuitable for applications requiring both high integration and selective programming.
Innovation Solution
A non-volatile memory device with unit cells serially connected and sharing word lines and bit lines, allowing for simultaneous programming and reading using tunneling methods, combining the advantages of both NAND and NOR types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If NAND type flash memory devices use Fowler-Nordheim tunneling method, then program speed is fast and integration rate is high, but random access is difficult and reading speed is slow
Solution Approach 1:
The memory device is divided into multiple memory blocks (first memory block, second memory block, etc.) with independent bit line pairs. This segmentation allows selective access to specific blocks, enabling fast reading of particular data regions while maintaining the overall NAND-type high-density structure. The bit line pairs (first bit line pair, second bit line pair) can be independently controlled to achieve block-level parallelism.
Solution Approach 2:
The patent introduces a new structural dimension by adding multiple bit line pairs and corresponding pass transistors to the conventional NAND structure. This creates a multi-dimensional access path where data can be read through different bit line combinations, enabling random access capability while preserving the vertical stacking that provides high integration.
2Speed
If NOR type flash memory devices enable easy random access, then reading speed is fast and selective programming is facilitated, but program speed is low and integration rate is low
Solution Approach 1:
The patent merges the advantages of both NAND and NOR structures by combining the high-density vertical stacking of NAND with the random access capability of NOR. The memory device integrates NAND-type charge trap memory cells arranged vertically with NOR-type selective access mechanisms through the bit line pair structure and pass transistor control, achieving both fast reading and fast programming in a single device.
Solution Approach 2:
The memory device achieves multi-functionality by enabling both fast programming through Fowler-Nordheim tunneling and fast reading through selective bit line access. The same memory structure supports both programming operations (with high efficiency) and reading operations (with random access capability), making the device universally applicable to various memory access patterns without requiring separate dedicated structures.
3Productivity
If NAND type flash memory devices use block erase characteristic, then erase speed is fast, but selective programming for specific cell is difficult
Solution Approach 1:
The patent applies local quality control through the pass transistor structure (first pass transistor, second pass transistor, third pass transistor) that can selectively enable or disable access to specific memory blocks or cells. This local control mechanism allows programming operations to be precisely targeted at specific cells or blocks while leaving other regions unaffected, enabling selective programming without requiring full block programming.
4Ease of operation
If NOR type flash memory devices use channel hot electron injection method, then random access is easy, but program efficiency is low and cell area is large
Solution Approach 1:
The patent replaces the channel hot electron injection mechanism with Fowler-Nordheim tunneling for charge storage. This substitution eliminates the need for high-voltage hot electron generation while achieving efficient charge trapping in the nitride layer. The tunneling mechanism provides higher programming efficiency and lower power consumption while maintaining the random access capability through the bit line pair structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high program efficiency and fast reading speeds while allowing for selective programming and high integration rates, overcoming the limitations of both NAND and NOR type flash memory devices.
Implementation Method 1
data is programmed in the selected memory transistor using tunneling of charges
Data Source
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AI summary
Provided is a non-volatile memory device which can overcome simultaneously drawbacks of an NAND type flash memory device and an NOR type flash memory device. The non-volatile memory device includes first and second bit lines connected to one string to cross the string. First and second memory transistors are included in the string between the first and second bit lines and respectively include a control gate and a storage node. A first pass transistor is included in the string between the first bit line and the first memory transistor and includes a first pass gate. A second pass transistor is included in the string between the second memory transistor and the second bit line and includes a second pass gate. A third pass transistor is included in the string between the first and second memory transistors and includes a third pass gate. A third bit line is connected to a channel of the third pass transistor. And, a word line is connected to the control gate of each of the first and second memory transistors in common.