Non-volatile Memory Serial Pipeline Phase Compensation
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Solution Overview
Problem
Non-volatile semiconductor memory devices operate at slower speeds compared to volatile devices, limiting their performance as system frequencies increase, and existing solutions fail to effectively eliminate phase differences between data and select clock signals, which impede high-speed data read operations.
Innovation Solution
A non-volatile memory device incorporating a combination of First In, First Out (FIFO) memory and a serial pipeline structure to compensate for phase differences between data and select clock signals, utilizing a hybrid pipeline method that includes a wave pipeline and a serial pipeline to enhance data read speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If non-volatile semiconductor memory device uses conventional data output structure, then device complexity is reduced, but read speed is limited and phase difference between data and select clock signal cannot be eliminated
Solution Approach 1:
The data output structure is segmented into multiple independent pipelines: a first pipeline for wave pipeline operation and a second pipeline for serial pipeline operation. Each pipeline can be independently controlled and optimized, allowing the system to achieve high-speed data output while maintaining manageable complexity through modular design.
Solution Approach 2:
The system dynamically switches between wave pipeline mode and serial pipeline mode based on operational requirements. The serial pipeline includes phase adjustment circuits that dynamically adjust the phase of data signals to eliminate phase differences with select clock signals, enabling adaptive optimization of read speed without permanently increasing device complexity.
2Productivity
If non-volatile memory device operates at higher frequencies, then productivity increases, but phase difference between data and select clock signal becomes more significant
Solution Approach 1:
The serial pipeline incorporates phase detection and adjustment circuits that monitor the phase relationship between data signals and select clock signals. When phase differences are detected, the system automatically adjusts the data signal phase to maintain synchronization, enabling high-frequency operation while preserving measurement precision through continuous feedback control.
Solution Approach 2:
The system performs preliminary phase adjustment of data signals in the serial pipeline before they reach the output stage. By pre-compensating for phase differences at lower frequencies in the pipeline, the system ensures that data signals are properly synchronized when operating at higher frequencies, preventing phase synchronization issues before they occur.
Data Source
AI summary
A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.