Nonvolatile Memory Plane-Dedicated Pad Sets for Parallel Data Transfer
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in increasing data transfer speeds and reducing power consumption, particularly in multi-plane structures where data multiplexing and signal routing lead to inefficiencies and increased power consumption.
Innovation Solution
The implementation of a nonvolatile memory device with a multi-plane structure that includes multiple memory planes and plane-dedicated pad sets, where each page buffer circuit is connected through bitlines to memory cells, and plane-dedicated pad sets are connected to page buffer circuits through dedicated data paths, allowing for parallel data transfer and reducing data multiplexing and signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data multiplexing and signal routing are used in multi-plane structures, then device integration is achieved, but data transfer delay increases and bandwidth is reduced
Solution Approach 1:
The memory device is divided into multiple independent memory planes, each with its own dedicated pad set. This segmentation allows parallel data transfer operations across different planes simultaneously, eliminating the need for data multiplexing and signal routing between planes, thereby reducing data transfer delay and increasing bandwidth.
2Loss of energy
If data multiplexing and signal routing are used in multi-plane structures, then device integration is achieved, but power consumption increases
Solution Approach 1:
The memory device is divided into multiple independent memory planes, each with its own dedicated pad set. This segmentation eliminates the need for complex data multiplexing and signal routing circuits, thereby reducing power consumption and device complexity while maintaining integration.
3Productivity
If plane-dedicated pad sets are implemented, then parallel data transfer is enabled, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple independent memory planes, each with its own dedicated pad set. This segmentation enables parallel data transfer operations across different planes simultaneously, improving productivity while the modular structure keeps the increased complexity manageable.
Solution Approach 2:
Each plane-dedicated pad set can handle multiple operations (read, write, erase) for its corresponding memory plane, providing universal functionality that simplifies the overall control logic despite the increased number of pad sets.
Data Source
AI summary
A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.