Non-volatile Memory Structure Mitigating Plasma Etching Damage
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Solution Overview
Problem
Transistor leakage in SRAMs limits power reduction due to plasma etching damage from the antenna effect during the fabrication of non-volatile memory components, particularly in resistive random access memory (RRAM) devices, which exposes a larger area to process plasma, leading to potential damage.
Innovation Solution
A non-volatile SRAM structure and fabrication method where a resistance-changing memory material covers only the second contact and not the first contact, with a top electrode contacting both, ensuring the area of the memory material is substantially larger than its interface with the second contact, thus minimizing plasma damage during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the control line is connected to the memory component in a conventional non-volatile SRAM structure, then the memory component can be integrated into the SRAM cell, but the control line exposes a much larger area to process plasma than the memory component itself, leading to plasma etching damage from the antenna effect
Solution Approach 1:
The patent divides the memory component into two separate parts: the memory element (formed in the semiconductor substrate) and the top electrode (formed as a separate conductive layer). This segmentation allows the memory element to have a small exposed area during plasma etching, while the top electrode is added later to complete the memory structure, thus reducing plasma damage to the memory component.
Solution Approach 2:
The patent performs preliminary actions by forming the memory element and its associated structures (tunnel barrier layer, blocking barrier layer, electrode) before forming the top electrode. This preliminary formation allows the memory element to be protected from plasma damage by limiting its exposure area, while the top electrode is subsequently added to establish the complete memory component functionality.
2Object-affected harmful factors
If the area of the resistance-changing memory material is reduced to minimize plasma exposure, then plasma damage is reduced, but the interface area with the contact must also be reduced, which may affect electrical connection quality
Solution Approach 1:
The patent applies local quality by creating a concentrated interface between the memory element and the contact, where the tunnel barrier layer and blocking barrier layer are localized directly over the contact opening. This localized structure ensures high-quality electrical connection in a small area, while the rest of the memory element has minimal exposure to plasma etching.
Solution Approach 2:
The patent transitions from a planar interface to a three-dimensional stacked structure, where the memory element is formed as multiple layers (tunnel barrier, blocking barrier, electrode) stacked vertically over the contact. This vertical stacking allows the interface area to remain small for reduced plasma exposure, while maintaining adequate electrical connection through the layered structure.
Data Source
AI summary
The disclosure provides a non-volatile memory structure and a method for fabricating the same. The non-volatile memory structure includes a first contact connected to a first transistor. A second contact is connected to a second transistor. A resistance-changing memory material pattern covers and contacts the second contact but not the first contact. A top electrode contacts both the resistance-changing memory material pattern and the first contact. An area of the resistance-changing memory material pattern is substantially larger than an area of its interface with the second contact.