Nonvolatile Memory Power Distribution via Segmented Tapping Regions
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in maintaining power stability and reliability due to the complexity of power distribution within their structures, particularly in three-dimensional flash memory devices where power supply and ground voltages need to be efficiently managed across multiple layers.
Innovation Solution
The implementation of a nonvolatile memory device design that includes a memory cell array with alternately disposed bit line and common source tapping regions, a page buffer with aligned bit line and tapping regions, and a mesh structure of conductive lines to distribute power supply and ground voltages, ensuring stable power delivery through a network of bit lines, page buffer tapping lines, and common source tapping lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional flash memory device structure is used to increase integration density, then storage capacity is improved, but power distribution complexity increases
Solution Approach 1:
The power distribution network is segmented into multiple independent tapping regions (first through fourth tapping regions) with separate tapping lines for power supply voltage and ground voltage. Each region handles specific cell groups, distributing the power management load across multiple localized segments rather than a single complex network, thereby reducing overall power distribution complexity while maintaining high integration density
Solution Approach 2:
The patent transitions from planar power distribution to a three-dimensional architecture where memory cells are stacked vertically across multiple layers. Power tapping lines are extended into the vertical dimension to serve cells in different layers, enabling high integration density while managing power distribution through multiple spatial dimensions rather than a single plane
2Reliability
If multiple tapping regions are added to improve power stability, then power distribution reliability is improved, but device structure complexity increases
Solution Approach 1:
Each tapping region is designed with dual functionality: it serves both as a power distribution node and as a structural template for organizing memory cells and bit lines. The tapping regions use consistent internal structures (tapping lines, contact holes, conductor patterns) that can be replicated across different regions, reducing design complexity while improving power stability through multiple distributed tapping points
Solution Approach 2:
The power distribution network is nested within the three-dimensional memory structure, with tapping lines integrated into the vertical stacking of memory cells. Contact holes and conductor patterns are nested within existing fabrication layers, allowing power distribution infrastructure to be embedded within the memory device structure rather than added as separate external components
Data Source
AI summary
Nonvolatile memory devices including memory cell arrays with first bit line regions and common source tapping regions which are alternately disposed on a substrate along a direction, a page buffer including second bit line regions aligned with the first bit line regions and page buffer tapping regions aligned with the common source tapping regions, and a plurality of bit lines spaced apart from one another and extending to the second bit line regions from the first bit line regions.