Nonvolatile Memory Trimming via Programmable Cell Redundancy
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Solution Overview
Problem
Existing semiconductor nonvolatile memory technologies, such as EPROM, face challenges in updating trimming and redundancy information after package assembly, leading to defects and increased production costs due to the need for dedicated masks and the inability to update information post-assembly.
Innovation Solution
A semiconductor nonvolatile memory design that includes a memory array with multiple nonvolatile memory cells, a sequence circuit for generating control signals, a write-read unit for storing and retrieving information, and a selection-drive unit for applying voltages to selected memory cells, allowing for the storage and retrieval of trimming and redundant information in a manner that enhances reliability and avoids simultaneous erasure or disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If laser fuse trimming is used to store trimming and redundancy information, then information can be stored in the memory chip, but the information cannot be updated after package assembly and all memory chips become defective when repair is needed
Solution Approach 1:
The patent changes the physical state of information storage from permanent (cut fuse) to reversible (programmable memory cell). By using memory cells that can be electrically programmed and erased, the trimming and redundancy information can be updated after package assembly, enabling post-manufacturing repairs and adjustments without rendering the entire chip defective.
Solution Approach 2:
The patent creates redundant copies of trimming and redundancy information in multiple memory cells. Instead of relying on a single fuse element, the information is stored in programmable memory cells that can be reprogrammed if defects are detected, providing backup copies that can replace defective information storage.
2Ease of manufacture
If a dedicated mask is used to mount the fuse element, then the fuse can be selectively cut, but production cost is increased
Solution Approach 1:
The patent uses standard memory cell structures and programming circuits that serve multiple functions: normal memory operation, trimming information storage, and redundancy repair. This eliminates the need for dedicated fuse masks and separate trimming equipment, as the same memory infrastructure handles all information storage and modification tasks.
Solution Approach 2:
The patent extracts the trimming and redundancy information storage function from the permanent fuse element and relocates it to programmable memory cells. This separation allows the use of standard memory fabrication processes without requiring additional dedicated mask steps for fuse integration.
3Adaptability or versatility
If trimming information is stored in memory cells, then information can be updated after assembly, but the memory area may be affected by simultaneous erasure or disturbance
Solution Approach 1:
The patent divides the memory array into distinct functional regions: normal memory cells for data storage and specific memory cells dedicated to storing trimming and redundancy information. This segmentation allows independent access and programming of trimming information without affecting normal memory operations, preventing simultaneous erasure or disturbance of critical trimming data.
Solution Approach 2:
The patent implements redundancy mechanisms where backup trimming information is stored in multiple memory cells. Before attempting to update trimming information, the system preserves existing valid copies as backup, providing a safety cushion against potential errors or disturbances during the programming process.
Data Source
AI summary
In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on. A write-read unit writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal. A latch circuit latches the predetermined information, read by the write-read unit, based on the latch selection signal. A selection-drive unit selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit, and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.