Non-Volatile Memory Programming With Dynamic Error Correction Logic
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Solution Overview
Problem
Semiconductor devices face inefficiency in utilizing memory space due to the need for error correction code calculations that require filling entire address units, even when only a portion of the data is meaningful, leading to wasted memory space when error correction logic is enabled.
Innovation Solution
Disabling error correction logic during incremental programming and enabling it later to allow efficient use of memory space by writing only the necessary data, thereby enabling partial page programming and maximizing memory utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction logic is enabled during programming, then data integrity is improved, but memory space utilization deteriorates
Solution Approach 1:
The patent segments the programming process into distinct phases: an initial phase where error correction is disabled for efficient data entry, and a subsequent phase where error correction is enabled for validation. This temporal segmentation allows each phase to optimize for its specific function, resolving the contradiction between speed/utilization and integrity.
Solution Approach 2:
The patent performs preliminary actions by disabling error correction logic during the data programming phase to maximize memory space utilization and programming efficiency. Only after the data is successfully programmed does it enable error correction logic for validation, ensuring data integrity without compromising the primary programming efficiency.
2Quantity of substance
If error correction logic is disabled during programming, then memory space utilization is improved, but data integrity deteriorates
Solution Approach 1:
The patent divides the programming operation into two segments: a first segment for programming data with error correction disabled to maximize space utilization, and a second segment for enabling error correction and performing validation. This segmentation allows the system to achieve both high memory utilization and data integrity.
Solution Approach 2:
The patent takes preliminary action by disabling error correction during the programming phase to optimize memory space utilization. After programming is complete, it enables error correction logic to perform validation, ensuring that data integrity is maintained through a subsequent check rather than during the primary programming operation.
3Reliability
If entire address unit is used for ECC calculations, then error detection capability is improved, but memory efficiency deteriorates
Solution Approach 1:
The patent applies partial action by using only the necessary portion of the address unit for data programming when error correction is disabled. The remaining bits that would otherwise be filled with default data are left unused during programming, improving memory efficiency. Error correction calculations are then applied only to the actual data portion, not the entire address unit, maintaining error detection capability without wasting memory space.
Solution Approach 2:
The patent changes the parameter of error correction logic operation by switching it between enabled and disabled states based on the programming phase. During programming, error correction is disabled to improve memory efficiency; during validation, it is enabled to ensure error detection capability. This dynamic parameter change allows the system to optimize for the current operational requirement.
Data Source
AI summary
Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.