Nonvolatile Memory Programming via Sequential Page Latching
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Solution Overview
Problem
Nonvolatile memory devices with multi-level cells (MLCs) face interference issues during programming operations, leading to suboptimal threshold voltage distributions and increased programming time due to the need to store multiple bits per memory cell, which affects data reliability and storage efficiency.
Innovation Solution
A method is introduced where data is programmed in a nonvolatile memory device by sequentially programming and latching data into logical pages, then transferring it to another memory block, minimizing interference by limiting simultaneous programming to up to two logical pages per word line, and using page buffers to manage and reset data effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC) programming is performed to store 3-bit information in one memory cell, then storage capacity is improved, but programming time and interference among neighboring cells increase
Solution Approach 1:
The patent divides the programming operation into multiple sequential stages, programming different logical pages (LSB, CSB, MSB) in sequence rather than simultaneously. This segmentation allows the system to program 3-bit information in MLCs while reducing interference among neighboring cells and managing programming time more effectively by breaking down the complex operation into manageable steps.
Solution Approach 2:
The patent loads and latches data into page buffers before actual programming occurs. This preliminary action prepares the data in advance, allowing the programming operation to proceed efficiently once initiated, thereby reducing overall programming time while maintaining the ability to store multiple bits per cell.
2Productivity
If multiple logical pages are programmed simultaneously in MLC, then programming throughput is improved, but interference among neighboring memory cells increases leading to threshold voltage distribution degradation
Solution Approach 1:
The patent segments the programming operation into sequential stages for different logical pages (LSB page, CSB page, MSB page). By programming these pages in sequence rather than simultaneously, the patent reduces interference among neighboring memory cells while still achieving effective programming throughput through efficient resource utilization and pipelining.
Solution Approach 2:
The patent employs periodic programming actions where different logical pages are programmed in alternating sequences. This periodic approach allows interference to subside between programming operations on neighboring cells, maintaining threshold voltage distribution integrity while still achieving high productivity through systematic alternation between different programming tasks.
3Reliability
If sequential programming of logical pages is performed to reduce interference, then data reliability is improved, but programming time increases
Solution Approach 1:
The patent loads and latches data into page buffers before the actual programming operation. This preliminary action prepares all necessary data in advance, so that when sequential programming begins, each stage can proceed without additional data preparation delays, thereby reducing the overall time penalty associated with sequential programming while maintaining data reliability.
Solution Approach 2:
The patent maintains continuous useful action by overlapping data preparation for subsequent logical pages during the programming of current pages. While one logical page is being programmed, the system continues to prepare and latch data for the next logical page in the sequence, ensuring that the sequential programming process does not include idle waiting time, thus reducing total programming time while preserving data reliability.
Data Source
AI summary
A method of programming a nonvolatile memory device includes sequentially programming first to (n−1)th logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n−1)th logical pages stored in a first physical page of the first memory block and latching the loaded data in first to (n−1)th latches of each of the page buffers, respectively, when receiving a second program command after programming all the first to (n−1)th logical pages, and latching new program data, received along with the second program command, in an nth latch of the corresponding page buffer and programming the data, stored in the first to nth latches of the page buffer, into a first physical page of a second memory block of the memory blocks.