Nonvolatile Memory Programming with Dynamic Bitline Shut-Off Timing
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Solution Overview
Problem
Nonvolatile memory devices with three-dimensional structures face increased disturbance of unselected memory cells during programming, affecting the efficiency of program operations.
Innovation Solution
A multi-pulse program scheme is employed, where the program voltage is applied multiple times with varying magnitudes, and the delay of the bitline shut-off signal is adjusted accordingly, increasing as the voltage increases, to enhance program efficiency and reduce disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the program voltage is applied to program selected memory cells in three-dimensional nonvolatile memory devices, then the programming operation can be performed, but disturbance of unselected memory cells increases
Solution Approach 1:
The patent applies dynamic voltage adjustment by varying the program voltage magnitude across multiple pulses (incremental step pulse programming) and dynamically adjusting the bitline shut-off signal delay based on the current program loop and pulse count. This dynamic control allows the system to adapt to changing program states, reducing disturbance to unselected cells while maintaining efficient programming of selected cells.
Solution Approach 2:
The patent employs periodic programming pulses applied to the selected wordline over multiple program loops. Each loop consists of multiple pulses with varying magnitudes, creating a periodic action pattern that gradually programs the selected memory cells while allowing recovery periods that reduce cumulative disturbance to unselected cells.
Solution Approach 3:
The patent applies preliminary action by implementing a bitline shut-off signal with a delay period before the bitline voltage is fully discharged. This preliminary shut-off action prevents excessive current flow and potential disturbance to unselected cells before the programming pulse completes, while still allowing effective programming of the selected target cell.
2Quantity of substance
If the integration degree and memory capacity of nonvolatile memory devices are increased using three-dimensional structures, then storage capacity improves, but disturbance of unselected memory cells increases
Solution Approach 1:
The patent applies local quality by selectively controlling the bitline shut-off timing for specific memory cells being programmed. The delayed bitline shut-off signal is applied locally to the page buffer associated with the selected wordline, ensuring that only the intended target cell receives the full programming effect while nearby unselected cells are protected from excessive disturbance through localized voltage control.
Data Source
AI summary
In a method of programming data in a nonvolatile memory device including memory cells and a page buffer, the memory cells are electrically connected to wordlines and bitlines, and the page buffer controls the memory cells. In a first program time period of a first program loop, a program voltage having a first program voltage is applied to a selected wordline that is electrically connected to a target memory cell, and a bitline shut-off signal having a first delay is applied to the page buffer. The program voltage is applied to the selected wordline multiple times during one program loop while a magnitude of the program voltage is changed. The delay of the bitline shut-off signal corresponds to a time period during which the bitline shut-off signal maintains a ground voltage.