Nonvolatile Memory Dynamic Write Pulse Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional nonvolatile semiconductor memories, such as SRAM, face challenges in reducing power consumption during write operations due to fixed write pulse widths, which do not account for varying write properties across memory cells, leading to inefficiencies and increased power usage.
Innovation Solution
A nonvolatile memory system that dynamically adjusts write pulse widths based on the specific write properties of each memory cell by monitoring and comparing the write current, allowing for immediate cessation of the write current once data is confirmed to be stored, thereby optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a fixed write pulse width is used for all memory cells, then the write operation can be completed for cells with good write property, but power consumption increases due to unnecessary extended pulse width for cells with worst property
Solution Approach 1:
The patent implements dynamic adjustment of write pulse width by introducing a write current detection circuit that monitors the write current in real-time. The write pulse width is dynamically shortened for memory cells that complete write operation early, while maintaining sufficient pulse width for cells with slower write property. This resolves the contradiction by making the write pulse width adaptive rather than fixed, reducing energy consumption without compromising write completion for all cells.
Solution Approach 2:
The patent employs feedback mechanism through the write current detection circuit that continuously monitors the write current and provides feedback signal to control the write pulse termination. When the detection circuit determines that write operation is completed (by detecting current threshold), it generates a feedback signal to terminate the write pulse early. This feedback-based control enables energy-efficient write operations by stopping the pulse exactly when needed, avoiding unnecessary energy consumption from extended pulse width.
2Loss of energy
If write pulse width is shortened to reduce power consumption, then energy efficiency improves, but write reliability deteriorates for memory cells with poor write property
Solution Approach 1:
The write current detection circuit provides real-time feedback on write operation status by monitoring current magnitude. The circuit compares the write current against a threshold to determine whether write operation is completed. This feedback mechanism ensures that the write pulse is terminated only when write operation is successfully completed, preventing premature termination that would compromise reliability. Memory cells with poor write property receive sufficient pulse width until their write operation completes, maintaining high write success rate.
Solution Approach 2:
The patent changes the write pulse width parameter dynamically based on the write current characteristics. Instead of using a fixed conservative pulse width for all cells, the system adjusts the pulse width parameter in real-time according to the actual write progress detected through current monitoring. This parameter adaptation allows optimal balance between energy efficiency and write reliability, ensuring each cell receives appropriate pulse duration for successful write operation.
3Reliability
If write pulse width is extended to ensure reliable write for all memory cells, then write reliability improves, but power consumption increases due to unnecessary extended pulse duration
Solution Approach 1:
The system transitions from static fixed pulse width to dynamic adaptive pulse width based on real-time write current detection. Memory cells with good write property experience early current threshold detection, triggering early pulse termination and reducing energy consumption. Cells with poor write property naturally receive extended pulse width until their write operation completes, maintaining reliability. This dynamic adaptation resolves the contradiction by matching pulse duration to actual write progress of each cell.
Solution Approach 2:
The write current detection circuit establishes a feedback loop that monitors write operation progress and controls pulse termination timing. The feedback signal generated when current threshold is reached ensures pulse termination occurs at the optimal moment - neither too early (compromising reliability) nor too late (wasting energy). This feedback-based timing control achieves the optimal balance between write reliability and energy efficiency for diverse memory cell characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reduced power consumption during write operations by setting optimal pulse widths for each memory cell, improving write durability and error rates while enhancing noise resistance in memory applications.
Implementation Method 1
a magnetoresistive element which has a resistance value changed in response to write current
Data Source
AI summary
According to one embodiment, a nonvolatile memory includes a memory cell, a write circuit generating a write current to change the memory cell from a first resistance value to a second resistance value, a first current generating circuit generating a first current based on the write current flowing through the memory cell, a second current generating circuit generating a second current based on the write current flowing through the memory cell, a hold circuit holding a first value generated based on the second current when the memory cell stores the first resistance value, a comparator comparing the first value with a second value generated based on a change of the first current while the memory cell changes from the first resistance value to the second resistance value, and a write current control circuit cutting off the write current based on a result of comparison of the comparator.