Nonvolatile Memory Quick Erase Mode for Timeout Reduction

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Solution Overview

Problem

Nonvolatile memory devices face challenges in efficiently managing erase operations, particularly in reducing erase time to prevent response delays and improve system performance, especially in three-dimensional memory devices like vertical NAND, where long erase times can cause write operation timeouts.

Innovation Solution

Implementing a method that allows for either a normal erase operation or a quick erase operation, where the quick erase operation sets memory cells to a pseudo erase state with a threshold voltage lower than a second erase verification level, reducing erase time and preventing response delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a normal erase operation is performed to set threshold voltage to a complete erase state, then data reliability is improved, but erase time increases causing response delays and write operation timeouts

Engineering Contradiction:

Improvedata reliabilityVSAvoiderase time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by introducing a pseudo-erase state that does not fully erase memory cells to the complete erase state, but instead sets them to a threshold voltage level sufficient for subsequent programming operations. This partial erasure reduces erase time significantly while maintaining adequate functionality for write operations, resolving the contradiction between complete erasure reliability and erase time efficiency

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent implements dynamic erase mode selection that adapts between normal erase and quick erase modes based on system conditions and requirements. The memory controller can dynamically choose the appropriate erase depth and verification level, allowing the system to optimize between reliability and speed depending on the specific operational context, thus resolving the static contradiction between complete erasure and fast erasure

Inventive Principle:

Principle #15Dynamics

2Manufacturing precision

If erase verification is performed at a higher verification level, then erase completeness is improved, but erase operation duration increases

Engineering Contradiction:

Improveerase completenessVSAvoiderase operation duration

Core Design Contradiction:

Manufacturing precisionVSDuration of action of moving object

Solution Approach 1:

The patent changes the verification parameter by introducing adjustable verification levels that can be set according to the desired erase depth. Instead of always using a fixed high verification level that ensures complete erasure, the system can lower the verification level for quick erase operations, thereby reducing the time required for verification while maintaining sufficient erase quality for the intended application

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9818485B2Nonvolatle memory device and memory system having the same, and related memory management, erase and programming methods

Publication Date: 2017.11.14 SAMSUNG ELECTRONICS CO LTD

AI summary

An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level.