Nonvolatile Memory Module RAM Data Validity Detection
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Solution Overview
Problem
There is a need for a semiconductor memory device that efficiently uses Random Access Memory (RAM) within a nonvolatile memory module while maintaining data integrity and compatibility with conventional interfaces, especially in scenarios where power supply interruptions occur.
Innovation Solution
A nonvolatile memory module that includes a RAM and a device controller with a DIMM controller, which allocates and de-allocates access areas during write and read operations, utilizing a DDR interface for communication between the host and the nonvolatile memory, and includes a status area to manage data validity and error correction, ensuring data integrity and efficient RAM usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a flash memory device is installed in a memory slot to improve communication speed, then communication speed between host and data storage is improved, but data integrity security and interface compatibility become concerns
Solution Approach 1:
A device controller is introduced as an intermediary component between the host and flash memory devices. This controller includes a DDR interface for high-speed communication with the host and manages data transfer to multiple flash memory devices, ensuring data integrity through controlled write operations and status monitoring while maintaining interface compatibility.
Solution Approach 2:
The device controller implements feedback mechanisms by monitoring the status of flash memory devices during write operations. When a write operation is initiated, the controller tracks the operation status and only allows host memory to be overwritten after confirming the write is complete, preventing data integrity issues while maintaining high communication speed.
2Speed
If a flash memory device is installed in a memory slot to improve communication speed, then communication speed between host and data storage is improved, but interface compatibility with conventional systems becomes a concern
Solution Approach 1:
The device controller provides universal interface functionality by implementing both a DDR interface for high-speed host communication and parallel flash memory interfaces for device communication. This multi-functional approach allows the system to achieve high communication speeds while maintaining compatibility with conventional flash memory interfaces and protocols.
3Quantity of substance
If RAM capacity is reduced to lower cost, then device cost is reduced, but efficient utilization of RAM during power interruptions becomes difficult
Solution Approach 1:
The host memory is segmented into multiple banks, and the device controller manages writes to specific banks based on operation status. This segmentation allows efficient utilization of limited RAM capacity by directing data to appropriate memory banks only when write operations are complete, preventing data loss during power interruptions without requiring large RAM capacity.
Solution Approach 2:
The device controller performs preliminary status checking of flash memory devices before allowing the host to overwrite memory. This preliminary action ensures that write operations are complete before memory is reused, enabling efficient RAM utilization with reduced capacity by preventing data integrity issues through advance verification.
Data Source
AI summary
The nonvolatile memory module includes at least one nonvolatile memory, and a device controller including a RAM to store data exchanged between a host and the at least one nonvolatile memory and a DIMM controller to control data exchange between the RAM and the at least one nonvolatile memory. An allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data.