Nonvolatile Memory Read Error Compensation via Adjacent Word-Line Sensing
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Solution Overview
Problem
Nonvolatile memory devices face increased read errors due to distortion in the intended threshold voltage distribution of memory cells, caused by factors like charge leakage, program disturbances, and word-line coupling, especially in three-dimensional structures with higher integration and capacity.
Innovation Solution
A nonvolatile memory device comprising a memory block with cell strings, a page buffer circuit, and a control circuit that performs multiple read operations to latch sensing data. The control circuit selects hard decision data based on the program state of adjacent word-line data and generates soft decision data to compensate for word-line coupling, enhancing error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory structure is adopted to increase integration degree and memory capacity, then memory capacity and integration degree are improved, but programming time increases and read errors increase due to word-line coupling and charge leakage
Solution Approach 1:
The patent divides the read operation into multiple segments: a first read operation to obtain initial sensing data, and a second read operation to obtain compensation data from adjacent word-lines. This segmentation allows the system to address read errors caused by word-line coupling by treating the main read and the compensation read as separate operations that can be processed independently and then combined.
Solution Approach 2:
The patent performs a preliminary action by conducting the second read operation on adjacent word-lines to obtain compensation data before finalizing the read result. This preliminary compensation read anticipates and addresses the word-line coupling effect that would otherwise corrupt the main read data, allowing the system to pre-correct for interference from neighboring word-lines.
2Adaptability or versatility
If three-dimensional memory structure is adopted to increase integration degree, then integration degree is improved, but programming time increases
Solution Approach 1:
The patent applies partial action by performing the second read operation only on adjacent word-lines that are likely to cause coupling effects, rather than reading all word-lines in the block. This selective approach provides sufficient compensation for word-line coupling while avoiding the excessive time cost of a comprehensive read of the entire memory block.
3Reliability
If multiple read operations are performed to compensate for word-line coupling, then read error rate is reduced, but operation time increases
Solution Approach 1:
The patent applies local quality by focusing the second read operation specifically on adjacent word-lines that are sources of coupling interference, rather than uniformly reading the entire memory block. This localized approach targets the specific problem area (adjacent word-lines causing coupling) and provides compensation where it is most needed, while minimizing the time cost by not reading unrelated areas.
Data Source
AI summary
A nonvolatile memory device includes a memory block, a page buffer circuit and a control circuit. The page buffer circuit is connected to the cell strings through bit-lines. The control circuit controls a read operation by: latching a first sensing data and a second sensing data in the page buffer circuit by performing a first read operation on a selected word-line designated by an access address based on a read voltage set; latching a third sensing data in the page buffer circuit by performing a second read operation on an aggressor word-line adjacent to the selected word-line, based on at least one adjacent read voltage; selecting one of the first sensing data and the second sensing data as a hard decision data based on a program state of the third sensing data; and generating a soft decision data by using the first sensing data and the second sensing data.