Nonvolatile Memory Read Mode Data Routing
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices face challenges in optimizing read speeds and data storage efficiency across multiple planes, particularly in transitioning between different read modes and handling data misalignment mappings.
Innovation Solution
A nonvolatile memory device architecture featuring a memory cell array with multiple planes connected to page buffer units and input/output units, where control logic manages data output through different input/output units in various read modes, allowing for efficient data storage and retrieval by dividing data across planes and utilizing multiple input/output units for faster data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored and read from multiple planes simultaneously, then read speed is improved, but device complexity increases due to multiple input/output units and control logic
Solution Approach 1:
The memory device is divided into multiple planes (first, second, third, and fourth planes) with dedicated page buffer units for each plane. This segmentation allows simultaneous read operations from different planes, improving overall read speed while distributing the complexity across modular units rather than concentrating it in a single complex circuit.
Solution Approach 2:
The first input/output unit is designed to handle data from multiple page buffer units (first, second, third, and fourth page buffer units), making it a multi-functional component. This universality allows the same input/output unit to serve multiple planes, improving read speed through parallel access while avoiding the need for completely separate I/O paths for each plane, thus managing device complexity more effectively.
2Productivity
If data is divided and stored across multiple planes, then storage efficiency is improved, but difficulty of detecting and measuring increases due to data misalignment mappings
Solution Approach 1:
Data is divided into separate data groups and stored in different planes (first data group in first and second planes, second data group in third and fourth planes). This segmentation improves storage efficiency by enabling parallel write operations across multiple planes. The control logic tracks which data group is stored in which plane, managing the complexity of data location through systematic organization rather than random distribution.
Solution Approach 2:
The control logic acts as an intermediary that manages the mapping between logical data groups and physical plane locations. It maintains information about which data group is stored in which plane and coordinates read/write operations accordingly. This intermediary function simplifies the detection and measurement of data locations by providing a centralized mapping mechanism rather than requiring complex distributed tracking across multiple planes.
3Productivity
If multiple input/output units are used for parallel data transfer, then productivity is improved, but device complexity increases due to additional control logic requirements
Solution Approach 1:
The first input/output unit is configured to receive data from multiple page buffer units (first, second, third, and fourth page buffer units) depending on the read mode. This multi-functional design allows a single input/output unit to handle data from multiple planes, improving productivity through parallel data transfer capabilities while avoiding the need for completely separate I/O units for each plane, thus managing device complexity more effectively.
Solution Approach 2:
The control logic dynamically configures the data transfer paths based on read mode. In first read mode, data is transferred from one page buffer unit through the first input/output unit. In second read mode, data is transferred from multiple page buffer units through both first and second input/output units. This dynamic reconfiguration allows the system to adapt its data transfer architecture to the specific read requirements, improving productivity when parallel transfer is needed while managing complexity through conditional activation rather than permanent complex wiring.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.