Nonvolatile Memory Read-Write Control Circuit for Power Stability
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices, particularly one-time programmable memories using fuse or anti-fuse elements, face challenges in preventing data loss and device malfunction due to unstable power supply conditions and radiation-induced errors, as existing protection circuits are complex and ineffective in preventing unauthorized write operations during power fluctuations.
Innovation Solution
A nonvolatile semiconductor memory device design that includes a read operation control circuit synchronized with an external clock for reading data, a write operation control circuit operating asynchronously with the external clock for writing data, and a reset circuit to reset the read operation control circuit upon receiving a write instruction signal, ensuring data integrity and preventing unauthorized writes by stabilizing the power supply and protecting against radiation-induced errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protection circuit with sequential circuit is used to prevent unauthorized write operations, then data security is improved, but circuit complexity increases and reliability decreases due to unstable operation during power fluctuations and radiation
Solution Approach 1:
The patent extracts the sequential circuit from the protection circuit, replacing it with a simple combination logic circuit. This removes the unstable flip-flop components while maintaining the authorization verification function through direct logic operations on the key signals, thereby reducing complexity and improving reliability during power fluctuations.
Solution Approach 2:
The protection circuit is segmented into separate functional blocks: key input registration, authorization verification logic, and write control. This modular approach allows each function to be implemented with simple logic circuits rather than a monolithic sequential circuit, reducing overall complexity and improving stability.
2Reliability
If a power-on reset circuit is added to stabilize the protection circuit, then initial state determination is improved, but the circuit cannot prevent malfunctions due to radiation and the reset operation is not stable
Solution Approach 1:
The patent applies preliminary anti-action by designing the protection circuit to be inherently immune to radiation-induced errors from the start. The combination logic circuit without sequential elements prevents radiation from causing unstable states, eliminating the need for power-on reset circuits that cannot adequately protect against radiation effects.
3Reliability
If synchronous read operation control is used with external clock, then read operation stability is improved, but write operation flexibility deteriorates due to asynchronous write control requirements
Solution Approach 1:
The control system is segmented into synchronous read control and asynchronous write control pathways. The read operation control circuit uses external clock synchronization for stability, while the write operation control circuit independently processes write requests without clock constraints, allowing each operation type to optimize for its specific requirements without compromising the other.
Data Source
AI summary
A nonvolatile semiconductor memory device includes a nonvolatile storage element to which data is inhibited from being rewritten, a read operation control circuit which captures a read operation instruction signal in synchronization with an external input clock, and a write operation control circuit to which a write operation instruction signal is input asynchronously with the external input clock. The read operation instruction signal gives an instruction to start a read operation to read data out of the nonvolatile storage element, and the write operation instruction signal gives an instruction to start a write operation to write data to the nonvolatile storage element. The device further includes a reset circuit which resets an operation of the read operation control circuit upon receiving the write operation instruction signal.