Nonvolatile Memory Ready State Control for Speed
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Solution Overview
Problem
Three-dimensional nonvolatile memory devices face challenges in achieving high operating speeds due to large resistive and capacitive components, leading to increased recovery times and potential delays in subsequent memory operations.
Innovation Solution
A nonvolatile memory device with a cell array of vertically extended cell strings, a page buffer for storing sensing data, a voltage generator for providing voltages to word and bit lines, and control logic to set the device to a ready state after data dumping, allowing for simultaneous data output during core recovery operations, thus preventing next command inputs until recovery is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional nonvolatile memory devices are used to meet high integration demand, then memory capacity is improved, but operating speed deteriorates due to large resistive and capacitive components
Solution Approach 1:
The memory device is divided into separate functional components: a cell array for data storage, a page buffer for data latching, an input/output buffer for data output, and control logic for managing operations. This segmentation allows data output operations to proceed independently from core recovery operations, enabling high-speed read operations without being bottlenecked by the recovery process.
Solution Approach 2:
The control logic sets the ready/busy signal to the ready state after sensing data is dumped to the input/output buffer, before core recovery is complete. This preliminary action allows the memory device to indicate readiness for the next command earlier, overlapping the data output process with the core recovery process and improving overall operating speed.
2Ease of operation
If traditional ready/busy signal control is used, then operational simplicity is maintained, but productivity deteriorates due to delays in subsequent memory operations
Solution Approach 1:
The ready/busy signal is transitioned to the ready state in advance (after data dumping to input/output buffer completes, before core recovery finishes), allowing the memory controller to issue subsequent commands without waiting for full core recovery. This preliminary signal transition improves productivity while maintaining the simplicity of the ready/busy control mechanism.
Solution Approach 2:
The memory device enables continuous operation by allowing the next command to be issued before core recovery is complete. The input/output buffer holds the sensed data ready for output while the core recovery proceeds in parallel, ensuring that the data output function continues without interruption and improving overall operational throughput.
Data Source
AI summary
A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.