Non-Volatile Memory Download With FSM-Based Reference Trimming
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Solution Overview
Problem
Existing methods for maintaining reference values during data download from non-volatile memory to local memory in ASICs are complex and increase ASIC area and startup time due to the use of dedicated reference blocks with auto-zeroing techniques, which are not suitable for rapid startup scenarios.
Innovation Solution
A method and circuit using pre-coded analog reference trims adjusted by a digital Finite State Machine (FSM) with a binary search-like methodology to quickly achieve accurate reference values, eliminating the need for complex auto-zeroing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated reference blocks with auto-zeroing techniques are used to maintain reference values, then reference value stability is improved, but ASIC area and startup time increase
Solution Approach 1:
The patent extracts the complex auto-zeroing function from a dedicated reference block and replaces it with a simplified digital Finite State Machine that implements binary search-like methodology. This removes the need for large analog reference blocks while maintaining reference value stability through algorithmic control of reference generator trimming.
Solution Approach 2:
The patent substitutes complex analog auto-zeroing circuitry with a digital Finite State Machine implementation. The FSM uses binary search-like methodology to quickly determine optimal trim values, replacing the mechanical/analog feedback loops with digital logic that achieves the same reference stability goal with reduced area.
2Reliability
If dedicated reference blocks with auto-zeroing techniques are used to maintain reference values, then reference value stability is improved, but startup time increases
Solution Approach 1:
The patent performs preliminary action by pre-programming the Finite State Machine with binary search-like methodology that可以快速 determine optimal trim values. The FSM is pre-configured with the algorithmic approach to systematically adjust reference generators, eliminating the need for time-consuming analog auto-zeroing sequences during startup.
Solution Approach 2:
The patent implements skipping by using the binary search-like methodology in the FSM to rapidly converge on optimal trim values. Instead of slowly adjusting reference values through analog feedback loops, the digital FSM skips through possible trim combinations systematically, achieving reference stability much faster during startup.
3Measurement precision
If complex auto-zeroing methods are used to maintain reference values, then reference value accuracy is improved, but device complexity increases
Solution Approach 1:
The patent substitutes complex analog auto-zeroing circuitry with a digital Finite State Machine implementation. The FSM uses binary search-like methodology to quickly determine optimal trim values, replacing the mechanical/analog feedback loops with digital logic that achieves the same reference stability goal with reduced area.
Solution Approach 2:
The patent changes the operational parameters from continuous analog adjustments to discrete digital trim values. The FSM controls reference generators by selecting from predefined trim levels, transforming the reference value adjustment from a continuous analog process to a discrete digital selection process, simplifying the overall system while maintaining accuracy.
Data Source
AI summary
According to an embodiment, a method includes adjusting a reference generator into a first configuration based on a temporary trim value resulting, in a first reference voltage and a first reference current being generated for a first memory. The method further includes performing an integrity check on an initial set of data downloaded from the first memory based on the first reference voltage and the first reference current. The initial set of data includes a first trim value. The method further includes downloading contents from the first memory into a second memory in response to a successful integrity check after adjusting the reference generator into a second configuration. In the second configuration, the reference generator generates a second reference voltage and a second reference current for the first memory. The reference generator is adjusted by the first trim value in response to a successful integrity check.