Non-volatile Memory Remote Redundancy Buffering
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Solution Overview
Problem
Conventional column redundancy schemes in non-volatile memory devices are slow and inefficient due to the need for multiple stages of logic and protection of redundant data within the memory chip, limiting data input/output rates and inefficient remapping of defective columns.
Innovation Solution
A remote redundancy scheme relocates redundant data from redundant data latches to buffer circuits, allowing a single addressing scheme for data exchange between the memory array and I/O bus, enabling more efficient utilization of redundant storage and faster data access by buffering substitute data in a central location accessible by all column circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional column redundancy schemes are used with redundant data stored in protected locations within the memory chip, then data security and reliability are improved, but data input/output rates decrease and access speed slows down
Solution Approach 1:
The patent extracts redundant data from the protected memory chip location and places it in an external buffer circuit. This separation allows the redundant data to be accessed faster through the buffer while maintaining the security of the original stored location, thus improving data access speed without compromising reliability.
Solution Approach 2:
The patent introduces a buffer circuit as an intermediary between the memory chip and the external interface. This buffer acts as a mediator that caches redundant data, enabling faster read/write operations while the main memory chip remains protected. The buffer circuit handles the speed-critical operations while the memory chip maintains security.
2Reliability
If multiple stages of logic are used for column redundancy protection, then data security is improved, but device complexity and processing overhead increase
Solution Approach 1:
The patent extracts the redundant data management functions from the complex internal logic of the memory chip and implements them in an external buffer circuit. This reduces the logic complexity within the memory chip while maintaining the same level of data security through the buffer's protection mechanisms.
Solution Approach 2:
The buffer circuit serves as an intermediary that simplifies the overall system architecture by handling redundancy management externally. This reduces the number of logic stages required within the memory chip itself, lowering device complexity while maintaining data security through the buffer's protected access pathways.
3Reliability
If redundant data is stored in protected locations within the memory chip, then data reliability is improved, but data input/output rates and storage utilization efficiency decrease
Solution Approach 1:
The patent extracts redundant data from the memory chip's protected locations and stores it in an external buffer circuit. This extraction enables faster data input/output operations through the buffer's high-speed interface while the original protected location remains secure, thus improving productivity without sacrificing reliability.
Solution Approach 2:
The buffer circuit acts as an intermediary that improves data input/output rates by caching redundant data in a high-speed location. This mediator enables rapid access to redundancy information without requiring slow access to the protected memory chip locations, thereby increasing overall system productivity while maintaining data reliability.
Data Source
AI summary
A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits.