Nonvolatile Memory Repair Circuit Using Redundancy Stacks
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Solution Overview
Problem
Conventional repair circuits for nonvolatile memory devices with vertically stacked memory cell arrays are inadequate in addressing the need for effective repair of defective memory cells.
Innovation Solution
A nonvolatile memory device with a stacked memory cell array and a repair control circuit that allows for the repair of defective memory cell groups using redundancy memory cell groups, either by replacing bit lines or word lines, within the same memory cell block, reducing the complexity and number of fuses required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional repair circuits are used for nonvolatile memory devices with vertically stacked memory cell arrays, then the repair process becomes complex and requires numerous fuses, but the fabrication yield is reduced
Solution Approach 1:
The memory cell array is divided into multiple stacks, with each stack containing memory cell groups organized by word lines and bit lines. The repair circuit segments the repair process by identifying defective memory cell groups within specific stacks and selectively replacing only the affected word lines or bit lines, rather than requiring comprehensive repair across the entire array. This segmentation reduces the number of fuses needed while maintaining repair effectiveness.
Solution Approach 2:
The patent introduces a vertical stacking dimension to the memory cell array organization, creating multiple layers of memory cell groups. The repair control circuit operates in this multi-dimensional space by identifying defective groups along the vertical stack dimension and selecting appropriate redundancy resources from the same or different stacks. This dimensional approach allows more efficient repair routing with fewer fuses compared to conventional planar repair circuits.
2Productivity
If redundancy memory cells are prepared for repairing defective memory cells, then the fabrication yield is improved, but the device complexity increases due to additional redundant components
Solution Approach 1:
Instead of providing comprehensive redundancy across the entire memory array, the patent implements local redundancy within each stack or memory cell group. Each stack contains its own redundancy word lines and bit lines that can be used to replace defective lines within that same stack. This localized approach reduces the total quantity of redundant components needed while maintaining the ability to repair defects, thereby improving fabrication yield without proportionally increasing device complexity.
Solution Approach 2:
The redundancy word lines and bit lines are designed to serve multiple functions: they can replace defective word lines or bit lines within their own stack, and can also be used to repair defects in other stacks through the repair control circuit's routing capabilities. This multi-functionality reduces the total number of redundant components required compared to dedicated one-to-one redundancy schemes, improving fabrication yield while controlling device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves the fabrication yield of nonvolatile memory devices by enabling efficient in-block repair of defective memory cells, reducing the need for redundant components and simplifying the repair process.
Implementation Method 1
The resistance level of the variable resistive element varies according to a voltage applied between the upper and lower electrodes
Implementation Method 2
a filament serving as a current path of a cell current is formed in the variable resistive element
Data Source
AI summary
The present invention provides a nonvolatile memory device that uses a resistance material. The nonvolatile memory device includes: a stacked memory cell array having a plurality of memory cell layers stacked in a vertical direction, the stacked memory cell array having at least one memory cell group and at least one redundancy memory cell group; and a repair control circuit coupled to the stacked memory cell array, the repair control circuit configured to repair a defective one of the at least one memory cell group with a selected one of the at least one redundancy memory cell group. The features that enable repair improve the fabrication yield of the nonvolatile memory device.