Nonvolatile Memory Power-On Reset Signal Timing Control

The patent applies preliminary action by delaying the power-on reset signal activation. A delay circuit is introduced that prevents the power-on reset signal from being activated until a predetermined time has elapsed after the power supply voltage reaches its normal level. This ensures that during sudden power-off events, the discharging signal is generated before the power-on reset signal, allowing word lines to be discharged before initialization occurs, thereby preventing data loss while maintaining reliable operation under normal conditions.

The patent introduces a delay circuit as an intermediary component between the power supply voltage detection and the power-on reset signal activation. This delay circuit acts as a mediator that compensates for the timing instability caused by PMOS transistor sensitivity to temperature and resistance variations. The delay circuit ensures consistent timing relationships regardless of environmental conditions, maintaining signal timing stability while preserving the simplicity of the PMOS-based power-on reset signal generation unit.