Non-volatile Memory Device Resisting Side-channel Attacks
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Solution Overview
Problem
Current security measures for ICs, such as cryptographic circuits, are vulnerable to side-channel attacks like Differential Power Analysis (DPA), which can compromise encryption keys, and Physically Unclonable Function (PUF) technologies face challenges in generating stable and secure digital ID data resistant to duplication and environmental errors.
Innovation Solution
A non-volatile memory device with resistive memory cells that transition reversibly among resistance value ranges based on electrical signals, using a read circuit to obtain resistance value information and an arithmetic circuit to calculate binary reference values, enabling secure and stable digital data generation for entity identification, resistant to side-channel attacks and duplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic circuits with encryption keys are used for security, then security protection against hacking is improved, but vulnerability to side-channel attacks like Differential Power Analysis increases
Solution Approach 1:
The patent introduces a non-volatile memory device as an intermediary component that generates digital ID data based on physical characteristics. This mediator replaces direct use of encryption keys in cryptographic circuits, thereby protecting against side-channel attacks while maintaining security functionality.
Solution Approach 2:
The patent replaces the traditional cryptographic circuit mechanism with a physical characteristic-based identification mechanism. Instead of using encryption keys processed through cryptographic algorithms, the system uses inherent physical properties of non-volatile memory cells to generate unique identifiers, substituting a vulnerable mechanical/electrical system with a physically unclonable system.
2Object-affected harmful factors
If PUF technology is used to generate digital ID data, then resistance to duplication is improved, but stability and security against environmental errors deteriorates
Solution Approach 1:
The patent changes the operational parameters of memory cells to generate digital ID data. By reading resistance values and comparing them against reference values, the system extracts stable digital identifiers that are resistant to both duplication and environmental variations. The parameter comparison approach filters out environmental noise while preserving unique physical characteristics.
Solution Approach 2:
The patent implements a feedback mechanism where digital ID data is generated by comparing physical characteristics against reference values. This feedback loop ensures that the generated identifiers remain stable across environmental variations while maintaining their unique identifying properties, thereby resolving the contradiction between duplication resistance and environmental stability.
3Object-affected harmful factors
If latest fine process technology is used to prevent probe attacks, then direct probing protection is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs the inherent physical characteristics of non-volatile memory cells themselves to provide security functionality. The memory cells' natural resistance variations serve as the security mechanism, eliminating the need for additional complex security structures or latest fine process technology. The system uses the memory cells' own physical properties for self-protection against probing attacks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a highly secure and stable digital ID data generation method, enhancing resistance to side-channel attacks and making it difficult to duplicate the chip, while reducing circuit overhead and power consumption, thus improving security for cryptographic applications.
Implementation Method 1
each of the memory cells having a resistance value and having a property that the resistance value reversibly transitions among resistance value ranges in a non-volatile manner in a variable state in accordance with application of different electrical signals
Data Source
AI summary
A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a write circuit. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information. In operation, the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells.