Non-volatile Memory Element with Resistance Switching
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Solution Overview
Problem
Existing latch circuits are volatile, requiring data to be reloaded when supply voltage is reapplied, which is time and energy consuming, especially in applications needing many latches to store data.
Innovation Solution
A non-volatile memory element comprising transistors and a resistance switching element, where the resistance switching element is programmed to represent a non-volatile data bit, allowing data to be stored without the need for continuous power, using a combination of transistors and control circuitry to manage data transfer and programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional volatile latch circuits are used, then the device complexity is low, but data must be reloaded when power is removed, increasing time and energy consumption
Solution Approach 1:
The patent applies preliminary action by pre-storing data in non-volatile memory elements before power removal. The resistance switching elements retain the programmed resistance states (representing data bits) even when power is removed, so that when power is reapplied, the data is already available and no reloading is needed. This resolves the contradiction by eliminating the time and energy required for data reloading while maintaining low device complexity.
2Reliability
If non-volatile memory elements are added to eliminate data reloading, then energy consumption and data reload time are improved, but the device complexity increases
Solution Approach 1:
The patent merges the volatile latch circuit functionality with non-volatile memory elements into a single integrated structure. The resistance switching elements are directly coupled to the latch circuit nodes, combining the data storage and retention functions in one unified circuit. This merging approach improves data retention reliability while minimizing the increase in device complexity by sharing circuit resources and integrating functions rather than adding separate independent components.
Solution Approach 2:
The resistance switching elements serve multiple functions: they act as non-volatile data storage elements, provide data retention during power removal, and interface directly with the volatile latch circuit. This multi-functionality improves reliability by ensuring data persistence while avoiding the need for separate dedicated non-volatile memory components, thereby limiting the increase in device complexity.
3Reliability
If resistance switching elements are programmed to store non-volatile data bits, then data integrity is maintained without power, but the manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes by programming the resistance switching elements to have distinct resistance states (first resistance value for logic 0, second resistance value for logic 1). These discrete resistance parameter changes represent binary data bits and are maintained without power. The use of clearly defined resistance parameter states ensures data integrity while the resistance switching mechanism is designed to achieve these states through standard programming techniques, managing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables quick and efficient loading of non-volatile data into volatile storage, reducing the need for frequent data reloading and minimizing energy consumption, with the ability to maintain data integrity even when power is removed.
Implementation Method 1
a first resistance switching element coupled in series with said third transistor and programmed to have one of first and second resistances representing a non-volatile data bit
Data Source
Figure 1~3
Figure 4~8B
Figure 7A~7B
AI summary
The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase.